Hibridni događaj

Program događaja

četvrtak, 26.5.2022 9:00 - 13:00, Bellavista, Grand hotel Adriatic, Opatija 9:00 - 9:45 Pozvano predavanje  M. Lukosius, R. Lukose, M. Lisker, G. Luongo, M. Elviretti, A. Mai, C. Wenger (IHP - Leibniz-Institut für innovative Mikroelektronik, Frankfurt Oder, Germany) Graphene Research in 200 mm CMOS Pilot Line   Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance. Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP. 9:45 - 12:00 Radovi  1. G. Luongo, R. Lukose, M. Lisker, M. Elviretti, A. Mai, C. Wenger, M. Lukosius (Leibniz Institute for High Performance Microelectronics, Frankfurt Oder, Germany) Graphene/metal contact resistance  Graphene is a bidimensional material that was first isolated in 2004 by Novoselov and Geim. His high electrical conductivity, high electron mobility and CMOS compatibility, make graphene an excellent material for the realization of a new generation of electronic devices [1]. Many works in literature have proven the advantages to use graphene as based materials in Schottky diodes, field effect transistors (GFETs), photo sensors and modulator [2]. Unfortunately, its diffusion in industry has been slowed by the difficulty to form a low resistance contact with the metals. Many works in literature reported the possibility to improve the conductivity by increasing the graphene/metal contact perimeter [3]–[5]. In this work, we investigated how the use of different contact patterns can improve the graphene/metal contact conductivity in proof-of-concept test structures: Transmission Line Measurement (TLM) and Cross-Bridge Kelvin (CBK). We observed that the use of different patterns can help to reduce contact resistance. [1] A. Di Bartolomeo, “Graphene Schottky diodes: An experimental review of the rectifying graphene/semiconductor heterojunction,” Phys. Rep., vol. 606, pp. 1–58. [2] G. Luongo, F. Giubileo, L. Genovese, L. Iemmo, N. Martucciello, and A. Di Bartolomeo, “I-V and C-V characterization of a high-responsivity graphene/silicon photodiode with embedded MOS capacitor,” Nanomaterials, vol. 7, no. 7. [3] J. T. Smith, A. D. Franklin, D. B. Farmer, and C. D. Dimitrakopoulos, “Reducing Contact Resistance in Graphene Devices through Contact Area Patterning,” ACS Nano, vol. 7, no. 4, pp. 3661–3667. [4] V. Passi et al., “Ultralow Specific Contact Resistivity in Metal–Graphene Junctions via Contact Engineering,” Adv. Mater. Interfaces, vol. 6, no. 1, p. 1801285, 2019. [5] M. Lisker et al., “Contacting graphene in a 200 mm wafer silicon technology environment,” Solid-State Electron., vol. 144, pp. 17–21. 2. M. Matić, T. Župančić, M. Poljak (Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Parallelized Ab Initio Quantum Transport Simulation of Nanoscale Bismuthene Devices  We describe our parallel ab initio quantum transport solver implemented in C programming language, with bismuthene nanoribbon (BiNRs) simulations used for the demonstration of its performance. The inputs are Hamiltonians obtained from ab initio density functional theory (DFT), which are wannierized into a localized basis to increase Hamiltonian matrix sparsity and to reduce the computational load without the loss of bandstructure accuracy. Numerical matrix operations are parallelized for cluster computation and optimized using Intel Message Passing Interface (MPI) and Intel oneAPI Math Kernel Library (MKL). We demonstrate that an acceleration of about ~45× is achieved through parallelization on 64 Xeon Silver CPU cores compared to a single-core execution. Finally, we investigate the electronic, transport and device properties of ultra-scaled bismuthene nanodevices. 3. M. Poljak, M. Matić, I. Prevarić, K. Japec (Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Bandstructure and Transport Properties of Semiconducting Gallenene Nanoribbons  We investigated the bandstructure and transport properties of semiconducting zig-zag b-gallenene nanoribbons (GaNR) using orbitally-resolved Hamiltonians and quantum transport simulations. The impact of GaNR width scaling on the bandstructure, transmission, bandgap and conductance is analyzed in detail. We find that GaNRs exhibit a nontrivial width-dependence of the conductance that is also nonsymmetric for electrons and holes. Moreover, bandgaps of up to ~0.95 eV are achievable by nanoribbon width downscaling. These results are explained by studying the width-dependent evolution of GaNR bandstructure. 4. M. Bendra, S. Fiorentini, J. Ender, R. Orio, T. Hadámek, W. Loch, N. Jørstad (Christian Doppler Laboratory for NovoMemLog at the Institute for Microelectronics TU Wien, Vienna, Austria), S. Selberherr (Institute for Microelectronics, Vienna, Austria), W. Goes (Silvaco Europe Ltd., Cambridhe, United Kingdom), V. Sverdlov (Christian Doppler Laboratory for NovoMemLog at the Institute for Microelectronics TU Wien, Vienna, Austria) Spin Transfer Torques in Ultra-Scaled MRAM Cells  Modern magnetoresistive random access memory (MRAM) cells with diameter of single-digit nanometer size utilize a combination of perpendicular interface-induced and shape-driven out-of- plane anisotropy in a free layer (FL) consisting of several ferromagnetic parts separated by tunnel barriers and/or nonmagnetic spacers. To accurately evaluate the torques acting in the structure we generalized the coupled spin and charge drift-diffusion transport approach to account for a number of tunnel barriers (TB) or spacers separating the elongated ferromagnetic pieces. The inclusion of the tunneling magnetoresistance effect is achieved by modeling the TB as a poor conductor with a conductivity locally dependent on the relative magnetization orientation of the ferromagnetic layers. The TB parameters are calibrated to reproduce the expected torque magnitudes in magnetic tunnel junctions (MTJ). To reproduce the spin transfer torques acting on a FL in a MTJs with several TBs and spacers, a special treatment of the spin current is proposed. In elongated FLs, position-dependent torques are present in the ferromagnetic pieces due to nonhomogeneous magnetization. We show that, with the proposed approach, composite FLs with several TBs are treated on equal footing. Our simulations of the magnetization dynamics in composite elongated FLs agree well with recent experimental demonstrations of switching of ultra-scaled MRAM cells. 5. B. Požar, I. Berdalović, F. Bogdanović, L. Marković, T. Suligoj (Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Layout-Dependent Noise Performance of Single-Photon Avalanche Diodes in 180 nm High-Voltage CMOS Technology  The paper describes the implementation and characterization of single-photon avalanche diodes (SPADs) fabricated in a commercial 180 nm high-voltage (HV) bipolar-CMOS-DMOS (BCD) technology. The SPAD structures utilize a deep, low-doped p-n junction as the avalanche multiplication layer, exploiting the high-voltage implant layers available in the technology. Technology computer-aided design (TCAD) simulations are performed to ensure that breakdown occurs in the active region of the device and to estimate the breakdown voltage and dark count rate (DCR). The devices are fabricated with different sizes and a circular, octagonal or square layout. The SPADs are characterized in terms of current-voltage (I-V) curves and dark count rates, both on bare dies as well as on dies bonded to a printed circuit board (PCB), by connecting them to an off-chip passive quenching circuit. Afterpulsing probability is analyzed by studying the distribution of interarrival times of dark pulses and comparing it to that of an ideal Poisson process. The circular and octagonal devices exhibit state-of-the-art noise performance with DCRs as low as 0.47 Hz/um2 at an excess voltage of 5 V, whereas the DCR of square structures increases by up to 2.7 times, partly due to afterpulsing effects at high excess voltages. 6. V. Kuznetsov, A. Fedorov (Nikolaev Institute of Inorganic Chemistry SB RAS, Novosibirsk State Technical University, Novosibirsk, Russian Federation), E. Tkachev (Nikolaev Institute of Inorganic Chemistry SB RAS, Novosibirsk, Russian Federation), B. Kholkhoev, V. Burdukovskii (Baikal Institute of Nature Management SB RAS, Ulan-Ude, Russian Federation) Composites of Polybenzimidazole with SWCNTs – Temperature Dependences of Resistance  Electron transport in composites based on dielectric polymer of polybenzimidazole and single-walled carbon nanotubes (SWCNTs) has been studied. The composites were synthesized by flow coating of dispersions (colloidal systems) of SWCNTs in solutions of polybenzimidazole in N-methyl-2-pyrrolidone. Concentration of SWCNTs in the composites was 1, 2, and 3 % (wt.). Electron transport in the film samples of the composites was studied by measuring and analyzing temperature dependences of the electrical resistance of the composites in the range from cryogenic temperature to 290 °C. It was shown that the higher SWCNTs concentration the weaker the dependences were. That is most likely due to a more significant contribution of metallic SWCNTs to the conductivity and weaker dependences correspondingly. 12:00 - 13:00 Radovi  1. T. Đuran, S. Tvorić, V. Šimović (Zagreb University of Applied Sciences, Zagreb, Croatia) Comparison of Efficiency Level for Induction Motor with Dahlander Winding in Direct on Line and via Frequency Converter Drive Connection  One of the main issues with AC machines i.e induction motors was speed regulation. In general, speed was mainly possible to regulate changing number of poles or frequency of supply voltage. Also smaller speed regulation was possible with changing voltage or load but this worked only for smaller ratio of drives so it will not be described here. Until frequency regulators (converters) reached certain level of development, both technical and economical, speed regulation was possible by changing number of poles. It was mainly done in one of two methods: Dahlander winding or separate windings in stator slots. One of deficiencies is that in Dahlander only combination of pole ratio is 2:1 e.g. 8 pole and 4 pole. Other is that speed is still constant depending on which number of pole you choose while when connected via frequency converter you can choose precisely at which speed i.e. frequency should the motor be rotating. In this paper, accent will be at measuring efficiency of the same motor when connected direct on line on a sine wave with different number of poles and using one pole number but driven via frequency converter and with speed regulation by changing frequency of supply voltage. 2. R. Babojelić, B. Vilić Belina, . Ileš, . Matuško (Faculty of Electrical Engineering and Computing, Zagreb, Croatia) FPGA Implementation of Set-based Model Predictive Control  This paper presents an field-programmable gate array (FPGA) implementation of a model predictive controller (MPC) based on one-step controllable ellipsoidal sets. Ellipsoidal sets are precomputed off-line, while the MPC optimization problem is solved in real time in FPGA hardware. For solving the optimization problem, a fast gradient projection method is used. The implementation of a controller is verified in a FPGA-in-the-loop simulation, showing the computational times in microsecond range. 3. K. Raič Raguž, M. Miletić, V. Zeleničić, D. Sumina, I. Erceg (Faculty of Electrical Engineering and Computing, Zagreb, Croatia), Ž. Nastasić (Databox, Zagreb, Croatia) Analysis of Current Harmonics in Data Center Power System  This paper presents power quality analysis at different points in a data center. Electrical distribution network scheme and data center description are also given. The method of measurements performed is briefly described and the results of real measurements of current and voltage Total Harmonic Distortion (THD) are presented and compared with IEEE 519-2014 recommended practice and requirements for harmonic control in electric power system. All measured values comply with the standard but measurements at downstream levels closer to the nonlinear loads have larger THD. četvrtak, 26.5.2022 15:00 - 19:00, Bellavista, Grand hotel Adriatic, Opatija 15:00 - 19:00 Radovi  1. D. Vinko, D. Bilandžija, L. Filipović (Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, Croatia) Drawbacks of Step Response Method for Detection of Foreign Metal Objects in Wireless Power Transfer System  Step response method is a method for detection of foreign metal objects in the proximity of the transmitter coil in WPT system. It is based on a measurement of the resonant frequency of the transmitter’s LC tank. As such, it can be used on the fly, while the wireless power transfer takes place, and it should have low impact on WPT system performance. This paper discusses drawbacks of the step response method with respect to required modifications of the transmitter and receiver circuits, and also the impact it has on the DC power supply through increased inrush currents. The discussion is verified through measurements on the built with implemented step response method. 2. D. Arbet, M. Kovac, D. Maljar, L. Nagy, V. Stopjakova (Faculty of Electrical Engineering and Information Technology, Bratislava, Slovakia) High Power Supply Rejection LDO Regulator for Switching Applications  The paper describes design and analysis of a Low-Dropout Regulator (LDO) with a high value of the power supply rejection (PSR) at high frequencies (above 10MHz). The proposed LDO was designed in a standard 65 nm CMOS technology. The output of the designed LDO can be adjusted by the voltage reference used in the LDO. The obtained results prove a very good PSR parameter at frequencies above 10 MHz, where the value of -40 dB is observed in the worst case. Additionally, the designed LDO topology exhibits promising load regulation properties even for a low value of the output capacitor. The proposed LDO can be fully integrated on a chip, and used in complex switching converter Systems on-Chip (SoC), where a high value of PSR is required. 3. J. Mikulić, G. Schatzberger (ams-OSRAM AG, Premstaetten, Austria), A. Barić (University of Zagreb, Zagreb, Croatia) Delay and Offset Compensated Relaxation Oscillator Core with Replica Integrator  This work presents a novel relaxation oscillator core architecture using a replica integrator and a chopped comparator suitable for advanced technology nodes. The oscillator core receives two reference voltages and three reference currents, based on which the output clock is generated having the frequency invariant to delay and offset of the comparators. The oscillator core prototype is designed in 110 nm technology, having an area of 0.045 mm2 and typically consuming 33 µA at 2 MHz. The frequency variation is ±0.5% in the temperature range from -40 to 125°C and ±0.33% in the power supply range from 1.08 to 1.32 V. The core starts up after a single half-cycle. 4. A. Žamboki, L. Gočan (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia), N. Bako, J. Mikulić, G. Schatzberger (ams-OSRAM AG, Premstaetten, Austria), A. Barić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Low-Power Frequency-Locked Loop Circuit with Short Settling Time  A phase-locked loop (PLL) is an important and commonly used electronic circuit in various electronic systems. Its main drawback is the use of an RC low-pass filter which takes up the majority of the PLL area on the chip. The RC low-pass filter is necessary to ensure the PLL stability. To mitigate this issue, a frequency-locked loop (FLL) is used because the stability of an FLL system depends on the Miller capacitance inside of the operational amplifier, which drastically reduces the capacitor size and thus the chip area. This paper presents the design of a fully integrated FLL based on a frequency-to-voltage converter (FVC). FVC is optimised so that it stabilises in just two clock cycles, which reduces the settling time of the entire FLL circuit. The voltage-controlled oscillator (VCO) is optimised for low power in all corners and for a wide input signal range. The circuit is implemented in a 180-nm CMOS process. Simulations show that the FLL circuit has a short settling time and a wide frequency range in all corners while using a small amount of power and chip area compared to the conventional PLL designs. 5. A. Traživuk, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia) 1-MHz Voltage-controlled Ring Oscillator Designed in 180-nm CMOS Technology for Implementation in Phase-locked Loop   This paper presents a voltage-controlled ring oscillator designed in 180-nm CMOS technology. Oscillator is designed for implementation in a phase-locked loop. Comparison between prelayout and postlayout simulation results as well as temperature and supply voltage dependence are described in the paper. Furthermore, technology corner and Monte Carlo analysis are performed. Finally, an overall specification of operation of the circuit regarding the change of work conditions is given. 6. J. Kundrata, I. Skeledžija, A. Barić (Faculty of Electrical Engineering and Computing University of Zagreb, Zagreb, Croatia) Voltage Regulation in an Integrated Controller of a Spread-Spectrum-Clocked Buck Converter  The switching converters sometimes use spread-spectrum technique to ensure the reduction of electromagnetic emissions by distributing the energy around the clock frequency and reducing its amplitude. The change of the clock frequency naturally causes the change of the output voltage if the duty cycle is not controlled properly, i.e. kept constant. This paper presents an architecture that consists of a phase-locked loop used to generate the spread-spectrum signal and a duty cycle control circuit that ensures the constant duty cycle and consequently constant out put voltage of a buck converter. These two circuits work in close co-operation to ensure smooth transition from one clock frequency to the next in order to keep the duty cycle as constant as possible. The operation of the controller circuit is explained as well as the function of each block in the controller. The operation of the phase-locked loop is presented together with several compensation techniques used to reduce the change of the duty cycle when the clock frequency is changed. An optimal set of parameters for the exponential optimization is found. 7. D. Tokić, D. Jurišić (University of Zagreb Faculty of Electrical Engineering and Computing, Zagreb, Croatia) High-Precision Fractional-Order Integrator for Generating Pink Noise from White Noise  For audio testing, a pink noise generator is a very useful and widely used tool for equalization of loudspeaker systems, room acoustics and crossovers. It can be built as a digital, analog or mixed circuit. The pink noise generator consists of a white noise source followed by a fractional order integrator (FOI) with a roll-off of 10 dB/decade. In this way, the obtained output power is constant in each decade, which is essential for testing audio devices within the entire audio frequency band. In this paper, an active realization of an FOI with an order 1/2 is presented, using an active-RC circuit that uses an operational amplifier as the active element. To build an FOI, we can use different approximation methods. We use our recently published Minimax method (MMX), with unequally (optimally) spaced singularities and compare it with a method proposed by other authors. The latter intuitively considers optimal singularities equally spaced on a logarithmic scale. We demonstrate the superiority of our proposed MMX approach. 8. M. Golubić, J. Kundrata, I. Skeledžija (Faculty of Electrical Engineering and Computing University of Zagreb, Zagreb, Croatia), D. Ciaglia, N. Pages, J. Fellner (ams-osram AG, Premstaetten, Austria), A. Barić (Faculty of Electrical Engineering and Computing University of Zagreb, Zagreb, Croatia) Automated Testing of Arm Cortex Based SoC with I3C Interface and Temperature Sensor  The Improved Inter Integrated Circuit (I3C) interface is a scalable, medium-speed, utility and control bus interface designed for connecting peripherals to an application processor. It is a backward-compatible successor to the I2C interface with increased speed, additional functionalities and improved energy efficiency. The Sensor Fusion project supports the early adoption of the I3C interface at the industry level by establishing a validation methodology of the timing parameters of the I3C interface and by setting up appropriate digital design workflows used in implementing I3C interface in Systems-on-Chip (SoC). The timing validation methodology is based on a Hardware-inLoop (HIL) topology, while the design workflows are represented by two I3C-based SoC examples: the autonomous I3C target and the temperature sensor integrated in Arm Cortex-M0 periphery with I3C Target interface. 9. I. Đurek, S. Grubeša, M. Suhanek, I. Leniček (University of Zagreb, Faculty of EE and Computing, Zagreb, Croatia) Comparison of New and Fast-Aged MEMS Microphones  MEMS microphones are increasingly used in systems exposed to open atmospheres. Therefore, it is important to test durability of these microphones. Two methods were used, one with a fast-aging process in a controlled environment chamber and by leaving microphones exposed to outside environment of a busy street. Their basic acoustic characteristics, especially sensitivity, were compared to new microphones. It was found out that treated microphones show slightly lower sensitivity than new microphones, which proves their suitability for use in open, non-controlled atmospheres. 10. R. Jõemaa, M. Grosberg, T. Rang, T. Pardy (Tallinn University of Technology, Tallinn, Estonia) Low-Cost, Portable Dual-Channel Pressure Pump for Droplet Microfluidics  Due to the high cost and complexity of instrumentation in droplet microfluidics, droplet generation has been limited to a small subset of the scientific community. In addition, scientific value is not in droplet generation, but rather in monodisperse microreactor environments created in droplets. To reduce the complexity of droplet generation, we designed a low-cost (~250 €), portable, dual-channel microfluidic pressure pump. In contrast with commonly used syringe pumps, our pump could control both phases in a two-phase flow simultaneously and pump continuously without refilling. Furthermore, it had wireless remote control and was battery-powered for portability. The pump was controlled through a dual core ESP32 DevKitC board, which enabled concurrent management of wireless access and flow control. Pressure setpoints could be configured remotely via Wi-Fi using a web browser based graphical user interface. Low-pulsation, continuous flows were produced by piezoelectric diaphragm pumps and regulated by closed-loop control of the pressure drop through the microfluidic chip. The pump could produce flow rates between 10-2050 μl/min for different liquid viscosities. Powered from its internal 3.7 V, 4 Ah battery, the pump could operate for >10 h at maximum load.

Marko Koričić (Croatia), Željko Butković (Croatia)

Slavko Amon (Slovenia), Dubravko Babic (Croatia), Maurizio Ferrari (Italy), Mile Ivanda (Croatia), Branimir Pejčinović (United States), Mirko Poljak (Croatia), Jörg Schulze (Germany), Tomislav Suligoj (Croatia), Aleksandar Szabo (Croatia), Davor Vinko (Croatia)

Popust se ne odnosi na studente doktorskog studija.

Marko Koričić
Fakultet elektrotehnike i računarstva
Unska 3
10000 Zagreb, Hrvatska

Tel.: +385 1 6129 671
GSM: +385 98 671 391
Fax: +385 1 6129 653
E-mail: marko.koricic@fer.hr

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