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Presented papers written in English and published in the Conference proceedings will be submitted for posting to IEEE Xplore.
| Chair: Tomislav Suligoj |
| Invited Paper |
P. Palestri, E. Caruso, F. Driussi, D. Esseni, D. Lizzit, P. Osgnach, S. Venica, L. Selmi (DIEG, Univ. of Udine, Udine, Italy)
State-of-the-Art Semi-Classical Monte Carlo Method for Carrier Transport in Nanoscale Transistors 
We review the Monte Carlo method to model semi-classical carrier transport in advanced semiconductor devices. We report examples of the use of the Multi-Subband Monte Carlo method to simulate MOSFETs with III-V compound semiconductor channel. Monte Carlo transport modeling of graphene-based transistors is also addressed.
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| Regular Papers |
L. Mikac, M. Ivanda, M. Gotić, D. Ristić, V. Đerek, H. Gebavi (IRB, Zagreb, Croatia), P. Gucciardi, S. Trusso, C. D'Andrea (IPCF CNR, Messina, Italy)
Preparation and Characterization of SERS Substrates: from Colloids to Solid Substrates
Surface enhanced Raman spectroscopy is an important technique for detection of wide number of analytes. Today, there is a growing need for the development of stable, sensitive, reproducible and portable SERS-active substrates for use in different fields. Some of the most extensively used SERS substrates are metal colloids because of their simplicity of preparation and strong Raman enhancement. However, the use of the colloid solutions for SERS deals with important issues, like stability and reproducibility. Other popular types of substrates are rough or nanoporous surfaces, such as porous silicon, coated with noble metals. Porous silicon (pSi) is a semiconducting material typically obtained by electrochemical etching in hydrofluoric acid (HF). After the etching, material is consisted of a network of pores with different diameters and depth, depending on the etching conditions. Due to its high surface-to-volume ratio this is an interesting material for photonic and sensing devices, drug delivery systems as well as for use in SERS. In this paper, attempts are made to prepare a stable and uniform noble metal colloidal solution as well as solid substrate using porous silicon (pSi) with deposited silver and gold nanostructures. SERS substrates obtained by different methods are evaluated for SERS efficiency using methylene blue and rhodamine 6G (R6G) at 514.5 and 633 nm. The prepared substrates showed good stability and reproducibility. For some substrates the concentrations detected were in the picomolar range.
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G. Yakovleva, A. Berdinsky (NSTU, Novosibirsk, Russian Federation), A. Romanenko (Nikolaev Institute of Inorganic Chemistry, Novosibirsk, Russian Federation), S. Khabarov (NSTU, Novosibirsk, Russian Federation), V. Fedorov (Nikolaev Institute of Inorganic Chemistry, Novosibirsk, Russian Federation)
The Conductivity and TEMF of MoS2 with Mo2S3 Additive
Transition-metal chalcogenides are prospective thermoelectric materials. One of it is a molybdenum disulfide MoS2, which has a layered structure. MoS2 has a good potential to have a high value of thermoelectric quality factor due to a high value of thermo-EMF and low value of thermal conductivity. But the low value of MoS2 electrical conductivity suppresses its thermoelectric quality factor ZT on the level of 0.4 at high temperatures. At present work it is shown the influence of addition of metal fracture with a high electrical conductivity to the original MoS2 material and influence of this addition in electrical conductivity and Seebeck coefficient (SC) of final mixture. Mo2S3 was chosen as a metal for addition. Mo2S3 has an electrical conductivity of 330 S/m and thermo-EMF of 10 μV/K at 300K. Bulk samples of MoS2 with addition of 3, 6, 10, 30 and 60 wt% Mo2S3 were chosen to study. An electrical conductivity of samples was measured in temperature range: 96 K – 423 K. All samples have shown semiconductor hopping conductivity with variable hopping length. The SC was measured in the temperature range of 300K-500K. The addition of Mo2S3 decrease SC from 200μV/K to 75μV/K.
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V. Kuznetsov, A. Berdinsky (Novosibirsk State Technical University, Novosibirsk, Russian Federation), A. Ledneva, S. Artemkina, M. Tarasenko (Nikolaev Institute of Inorganic Chemistry, Novosibirsk, Russian Federation), V. Fedorov (Novosibirsk State University, Novosibirsk, Russian Federation)
Strain-Sensing Element Based on Layered Sulfide Mo0.95Re0.05S2
The work presents a study of piezoresistive effect of thin films of rhenium-doped molybdenum disulfide of composition Mo0.95Re0.05S2 possessing layered structure of 2H-MoS2 type. The compound was synthesized by high temperature ampoule method using stoichiometric mixture of elements. The thin films were formed by spraying colloidal dispersion produced by liquid exfoliation of solid phase in mixed solvent EtOH/H2O. The phase Mo0.95Re0.05S2 is semiconductor with effective activation energy of about 150 meV estimated from temperature dependences of resistance of the films. The dependence of resistance on deformation is presented. It has almost linear type and good reproducibility during a sinusoidal alternating load of 0.01% deformation amplitude. The strain gauge factor of 12 was obtained from room temperature measurements using a beam of uniform strength (in bending).
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V. Tudić (Veleučilište u Karlovcu, Karlovac, Croatia)
Electrical Properties of Composite Silicon Thin Films
Amorphous-nano-crystalline silicon composite thin films (a-nc-Si:H) samples were synthesized by Plasma Enhanced Chemical Vapor Deposition technique. The electrical properties of thin films and measurement of DC conductivities were accomplished using Dielectric spectroscopy (AC Impedance Spectroscopy) in wide frequency and temperature range. The X-ray diffraction and high resolution electron microscopy measurement showed that films consist of isolated nano-crystals embedded in amorphous matrix. In analysis of impedance data, two approaches were tested: the Debye type equivalent circuit with two paralel R and CPEs (constant phase elements) and modified one, with tree paralel R and CPEs including crystal grain boundary effects. It was found that the later better fits to experimental results properly descibes crystal grains dielectric effect and hydrogen concentration indicating presence of strain. The amorphous matrix showed larger resistance and lower capacity than nano-crystal phase. Also it was found that copmosit silicon thin film cannot be properly descibes by equivalent circuit only with resistors and constant phase elements in serial relation.
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S. Krivec, M. Poljak, T. Suligoj (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Impact of Different Gate Insulator Materials on the Electron Mobility in Ultra-thin (100) InGaAs-on-insulator MOS Devices
In this paper, we studied the influence of the parameters of technologically relevant dielectrics (SiO2, Al2O3 and HfO2) and channel thickness downscaling on the electron mobility in InGaAs-on-insulator channels with (100) surface orientation. The study of mobility properties is enabled by a self-consistent Schrödinger-Poisson solver that is coupled with a scattering simulator based on the momentum relaxation time approximation, in order to calculate the scattering rates of electrons with acoustic, optical, remote and polar phonons, surface roughness, Coulomb impurities and alloy disorder. Simulations revealed that SiO2 is the optimum gate dielectric material irrespective of the body thickness, followed by Al2O3 or HfO2, depending on InGaAs-to-oxide surface roughness.
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M. Koričić, J. Žilak, T. Suligoj (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Impact of the Emitter Length Scaling on Electrical Characteristics of Horizontal Current Bipolar Transistor with Single Polysilicon Region
Emitter length scaling of HCBT with single polysilicon region is investigated by 3D device simulations with the emphasis on the high frequency characteristics. It is shown that collector current and junction capacitances scale linearly with the emitter length. Cut-off frequency is improved for small emitter area devices due to current spreading in the collector region which reduces the current density and causes the base push-out at higher collector currents. The effect cannot be captured by scalable transistor model and separate set of model parameters is needed for transistors with very small emitter size.
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I. Janeković, T. Knežević, T. Suligoj (Faculty of Electrical Engineering and Computing, Zagreb, Croatia), D. Grubišić (Laser Components DG, Inc., Tempe, Arizona, United States)
Optimization of Floating Guard Ring Parameters in Separate-Absorption-and-Multiplication Silicon Avalanche Photodiode Structure
In this paper, the effect of the floating guard ring (FGR) parameters such as number of FGRs and the distances between the FGRs on the prevention of the breakdown at the multiplication layer edge for a given avalanche photodiode (APD) structure has been analyzed. Four structures are examined: APD without FGR and APDs with one, two and three FGRs. The width and depth of the boron-doped FGRs is 1 µm with peak concentration of 1018 cm-3. The intrinsic breakdown voltage in the active region of the APD is 371 V and the structure is fully depleted at 14V. Edge breakdown of the APD structure has been prevented using three FGRs. Optimal positions of the three FGRs are determined for achieving breakdown voltage of 409 V at the multiplication edge compared to the edge breakdown voltage of 170 V, 270 V and 348V for structures without floating guard rings, with one FGR and with two FGRs, respectively. Spectral responsivity of the structure is analyzed in the range of 400 to 1000 nm showing that such APD can be effectively used for detection of the visible light.
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| Chair: Dubravko Babić |
| Regular Papers |
C. Popa (UPB, Bucharest, Romania)
Low-Power Low-Voltage CMOS Analog Signal Processing Circuits Using a Functional Core
The paper presents an original approach of designing analog signal processing circuits, based on the re-using of the same functional core for implementing a multitude of circuit functions: signal gain with theoretical null distortions, signal squaring, voltage multiplying with very good linearity and simulation of a perfect linear resistor with both positive and negative equivalent resistance. The great advantages of the increased modularity and controllability and of the reduced design costs represent an immediate consequence of the multiple functions realized by the proposed structures. Because the most important circuit complexity is concentrated in implementing the core of the multifunctional structure, both circuit area and power consumption per each realized function can be strongly reduced using this method, especially for multifunctional structures that are able to implement an important number of functions. The overall error of the linear designed computational structures is 0.4% and the approximation error for the squaring circuit is 0.27%, in the condition of a low-voltage low-power operation (a supply voltage of 1.5V and a medium current consumption of 50mA for each implemented circuit function).
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c. popa (UPB, Bucharest, Romania)
Multifunctional Circuit Using Improved Performances Linearization Technique
Original low-power low-voltage multifunctional structure with improved performances will be presented, allowing to implement (with minor changes in the design) two important functions: signal gain with theoretical null distortions and voltage multiplying with very good linearity. The great advantages of the increased modularity and controllability and of the reduced design costs associated represent an immediate consequence of the multiple functions realized by the proposed structures. The linearity is strongly increased by implementing original techniques, while the silicon occupied area per function is reduced as a result of the proposed multifunctionality. The structures are implemented in 0.35um CMOS technology and are supplied at +/- 3V. The circuits present a very good linearity, correlated with an extended range of the input voltage (at least +/- 0.5V).
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S. Pashmineh, D. Killat (Brandenburg University of Technology, Microelectronics Department, Cottbus, Germany)
Design of a High-Voltage Differential Amplifier Based on Stacked Low-Voltage Standard CMOS with Different Input Stages
This paper presents the design of a high-voltage differential amplifier using six different pre-input stage circuits to reduce high-voltage input levels to low-voltage signals. The proposed circuits are designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and a supply voltage of 5 V. The designs are based on stacked low-voltage standard CMOS transistors. The different pre-input stage circuits are compared to each other in terms of their circuit description, drawbacks, advantages and simulation results. The principle of the five designed pre-input stage circuits can be applied to higher voltage range input signals as well.
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A. Pajkanovic, V. Malbasa (Faculty of Technical Sciences, University of Novi Sad, Novi Sad, Serbia)
Opamp Based Bandgap Voltage Reference in 130 nm: Design and Schematic Level Simulation
A bandgap voltage reference circuit employing an operational amplifier is designed using the unified current-control model transistor model and 130 nm CMOS standard process. Schematic level simulations in Cadence Design System Spectre Simulator show temperature variation of the output voltage within 0.43 mV over a temperature range of 165 K (from -40 C up to 125 C) in the nominal case, i.e. ±1.12 ppm/°C. The supply voltage (3.3 V) change of ±10% causes a disturbance in the output voltage of only 2.38 mV, i.e. 0.1 % of the output nominal value. The process variations, examined through corner and Monte Carlo analysis, are also presented and discussed.
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N. Bako, Ž. Butković, A. Barić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Design of a Power Supply and Voltage References for a Wirelessly Powered ADC in 0.18-µm CMOS
A low power tag with integrated ADC designed in 0.18-µm CMOS process is presented. The tag extracts energy from electromagnetic waves and stores the charge on external capacitor. The stored charge is used to supply the tag circuitry: supply unit, current and voltage references and voltage regulators and ADC. The obtained referent voltage shows good stability over process, voltage and temperature variations. The mean value of the reference voltage is 485.8 mV and the standard deviation is σ = 7 mV in the temperature range -10 °C to 70 °C. The mean temperature coefficient (TC) is 7 ppm/°C and the standard deviation is σTC= 30 ppm/°C in the same temperature range. The differential nonlinearity (DNL) of the ADC is 0.075/-0.18 LSB and the integral nonlinearity (INL) is 0.22/-0.2 LSB respectively. The dynamic characteristics are following: SFDR is 66 dB, SNDR is 52 dB and ENOB is 8.35. The overall power consumption is 22 µW and the active area is 0.96 mm2.
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I. Broz (Locus Ltd, Zagreb, Croatia), N. Bako, Ž. Butković, A. Barić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
RFID UHF Protocol Implementation in Distributed Sensor Networks
In today’s market significant segment is related by the applications using sensors to track physical events in the surrounding environment. Market share related to the distributed sensor networks based on the wireless communications (like Internet of Things IoT devices) is particularly increasing. One of the hardest challenges in that field is associated with the power supply requirements. Battery operated electronics is limited by the battery capacity and the battery lifetime. This paper proposes solution based on the RFID EPC Gen2-protocol-based readers supplying power to the sensor nodes, consisting of the microelectronic circuit and the associated sensor. Besides the power, RFID protocol provides means of wireless communication without the need for the battery supply on the sensor node side. Analogue circuits for receiving and demodulating RF ASK modulated signal from the reader and transmitting back the signal to the reader using backscattering technique are presented. A subset of the command protocol is implemented to support data communication including sensor identification through the unique ID code and sensor reading in the form of the digital word provided by the on-chip ADC. RTL description of digital control is developed in VHDL and synthesized. The prototype is designed in the UMC Mixed-Mode/RF 180 nm technology.
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M. Šprem, D. Babić, M. Bosiljevac, Z. Šipuš (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Temperature Dependence of Injection-Locked Fabry-Pérot Laser Emission in WDM-PON Architectures
We investigate the influence of temperature on multimode Fabry-Pérot laser output in a proposed colorless WDM system with self-seeding via modulation averaging reflector and with BLS-seeding. In particular, we investigate the connection between the information about the optical laser output from the laser integrated monitor photodetector and optical power output of the entire system with temperature change of the laser diode.
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B. Igrec (Faculty of Mechanical Engineering and Naval Architecture, University of Zagreb, Zagreb, Croatia), M. Bosiljevac (Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia), S. Rudan (Faculty of Mechanical Engineering and Naval Architecture, University of Zagreb, Zagreb, Croatia), Z. Šipuš, D. Babić (Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia)
Fiber-Optic Vibration Sensor for High-Power Electric Machines
A fiber-optic sensor for monitoring mechanical vibrations in high-power electric machines has been demonstrated using 3D-printing. The paper will describe the design, mechanical and optical modeling, and results of preliminary characterization.
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J. Kundrata, A. Barić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Comparison of Electrical and Electromagnetic Properties of a Planar Inductor
This paper compares the electromagnetic and electrical properties of a planar inductor used in a low-profile OLED driver. A luminary consists of the OLED cell and its driver which uses a planar inductor. The proximity of the OLED cell and the constrained area makes the planar inductor lossy. The planar inductor represents a loop antenna and a main source of radiated emissions of the driver. The properties of the planar inductor are analysed w.r.t. the quality factor and the magnetic moment. The analysis uses a two-level experiment based on EM simulations to explore the geometrical parameters of the inductor. The experiment shows that the track width and the fill-ratio of the inductor have the greatest effect on its properties. It is concluded that a planar inductor which introduces minimum power losses and radiated emissions to the OLED driver needs to be optimized w.r.t. the track width and the fill-ratio.
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F. Fajdetic, M. Mikic, T. Mandic, A. Baric (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Effects Influencing Repeatability of Direct Power Injection Measurements
The electromagnetic compatibility (EMC) performance of the voltage regulators is the significant factor in the EMC performance of the complete system. In this paper the characterization of the voltage regulator by direct power injection (DPI) method is presented. Although, the DPI method is well defined by several standards, the repeatability of the measurement can be compromised by various factors. The DPI method measurement results are presented for the L4949 voltage regulator. The repeatability of the method is assessed by variation of various factors related to the operating point of the voltage regulator and to the measurement set-up. The obtained results are compared to the results presented by other authors.
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R. Blecic (University of Zagreb, Zagreb, Croatia), R. Gillon (ON Semiconductor, Oudenaarde, Belgium), B. Nauwelaers (KU Leuven, Leuven, Belgium), A. Baric (University of Zagreb, Zagreb, Croatia)
SPICE Analysis of RL and RC Snubber Circuits for Synchronous Buck DC-DC Converters
Operation of a 1.3-MHz, 12-to-1.2 V, 20-A synchronous buck converter is analyzed by SPICE simulations. Special attention is given to two resonances formed by the capacitance of FETs in the off-state and the total inductance of the input decoupling network. The resonances are the main source of the broadband electromagnetic (EM) interference. Two most common circuit level methods for reducing the EM interference, an RL snubber circuit and an RC snubber circuit, are analyzed and compared in terms of their impact on the radiation characteristics, efficiency and reliability of the analyzed synchronous buck converter.
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F. Hormot, J. Bačmaga, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Dual-channel Programmable Precise Time-delay Pulse Signal Generator for Synchronous DC-DC Converter Applications
A precise two-channel programmable time-delay pulse signal generator for synchronous DC-DC converter applications is presented. The developed system is required to generate high-side (HS) and low-side (LS) signal in frequency range from 1 MHz to 15 MHz and duty cycle values from 5% to 50%. While both generated signals have the same switching frequency, the pulse width and time-delay of each signal is adjusted independently of the other signal. The most notable characteristic of the developed generator is the ability to adjust dead-times between the generated signals as precise as possible in order to use the signal generator for testing the semiconductor devices for synchronous DC-DC converter applications. The developed signal generator has the ability to set the pulse width and time-delay with the precision of 250 ps. The system is designed to transmit generated signals using either the BNC or optical fiber cable. The functionality of the system is verified by measurements performed under various operating conditions.
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| Chair: Željko Butković |
| Regular Papers |
I. Mrčela, V. Šunde, M. Kovačić (University of Zagreb Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Effect of Dead Time and Semiconductor Device Voltage Drops of Output Voltage of Multilevel Converters
This paper presents the results of a research of the influence dead time and finite semiconductor devices' voltage drops have on the output voltage of three-level neutral-point clamped power converters. This paper shows that finite voltage drops cause a DC voltage shift, while dead time causes spectral degradation, i.e. lowers the base harmonic amplitude and causes a larger total harmonic distortion value. This influence was analytically analyzed and the results were confirmed via simulation models. The influence voltage drops have was confirmed using Ansys Simplorer, while the influence dead time has was confirmed using Matlab. The influence voltage drops' thermal dependence has on the output voltage was also confirmed using Simplorer. The paper shows that the three-level neutral-clamped converters' output voltage is dependent on the listed parameters and suggests a method to suppress the negative effects these parameters have on the converter voltage.
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M. Novak, V. Šunde, Ž. Jakopović (University of Zagreb Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Model of Three Level Neutral Point Clamped Converter (NPC) for Grid Connected Photovoltaic Systems
Photovoltaic modules as direct converters of solar energy into electrical energy are typically connected to the power grid trough standard two level converters. A photovoltaics system can be connected to the power grid if it can satisfy the IEEE standardized conditions set by the power grid operator. The conditions include limitations of THD factor and current harmonics. Multilevel converters which have a lower THD factor than two level converters can satisfy these conditions and in the same time work at higher switching frequencies lowering the losses and the size of the output filter. The model implemented in Simulink® MATLAB consists of a photovoltaic array, boost dc-dc converter with MPPT control and three level neutral point clamped converter connected to the power grid. The simulation results are presented, analyzed and compared to the standard model with a two level converter to validate the benefits of the usage of multilevel converters for grid connected photovoltaic systems.
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I. Musulin, J. Babić (Končar–Electrical Engineering Institute Inc., Zagreb, Croatia), Ž. Jakopović (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Fast Development of a DSP-Based Control of Three-Phase Four-Leg Inverter for Auxiliary Power Supply Converters Using Hardware-in-the-Loop
This paper presents an easy and relatively fast way to design and implement control system of three-phase four-leg inverter in DSP (digital signal processor). The inverter model is emulated using hardware-in-the-loop simulator and control system is coded in TI DSP identical to the target system using graphically based block-diagram programming environment. A multi-loop cascade control is applied and two control strategies are implemented: i) the PI (proportional-integral) controllers with symmetrical sequence current and voltage decomposition and ii) the PIR (proportional-integral-resonant) controllers. Experimental results with symmetrical and single-phase loads are presented. The control algorithms are evaluated based on the execution time. Results show that PIR based control executes roughly three times faster that PI control.
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I. Volarić, N. Stojković, S. Vlahinić (Faculty of Engineering , Rijeka, Croatia)
Noise Improvement Using SC Filters
In this paper noise analysis of three different filter designs is performed. Voltage noise spectral density and RMS noise voltage in simply designed active RC, noise optimized active RC and switched capacitor (SC) filter design are calculated for fifth order Chebyshev low pass filter, with a cut-off frequency fc=3.4kHz, and pass-band ripple αmax=-0.5dB. All three designs are realized as a cascade of two second order sections and one first order section. All filter analysis has been performed using MATLAB and SPICE program tools. Through the analysis it is shown that SC based filter has significantly lower noise when compared with active RC based filter.
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M. Adnan (Carinthian Tech. Research AG, Villach, Austria), D. Hammerschmidt (Infineon Technologies AG, Villach, Austria), M. Huemer (Johannes Kepler University, Linz, Austria)
Phase Demodulation of Magnetic GMR Signal for Virtual Sensing Applications by using Hilbert Transform
GMR sensors, which are used in conjunction with magnetic encoders (magnetic pole wheels), have a huge number of applications in automotive and machine industry, where they are used to compute the rotational speed of rotating parts like wheels and shafts. In this paper, we present an analytical model of magnetic pole wheel signal as it is sensed by a GMR sensor. Experimental measurements are performed to check the validity of the mathematical model. Furthermore, we present a novel digital signal processing technique, which incorporates the Hilbert transformer to phase demodulate this GMR signals to compute high resolution instantaneous position and speed information. A frequency domain analysis is then deployed to analyze the signal for any low frequency vibrations present in the rotating part.
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W. Brenner, N. Adamovic (Vienna University of Technology, Vienna, Austria)
Thin-film CIGS Solar Modules for Design Driven Applications in the Frame of the FP7 NMP Project SolarDesign
Abstract - The FP7 NMP project SolarDesign addresses the demand for aesthetically integrated photovoltaic materials by the development of novel solar cell materials, manufacturing processes and supportive actions (design toolbox). One key technology is a laser based monolithic interconnection process for thin-film solar cells.
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D. Ćika (Research and Engineering Center d.d., Zagreb, Croatia), T. Martinović, H. Džapo (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Measurement System for Object Detection Based on Multielectrode Capacitive Sensor
The problem of detecting objects, people and events is encountered in different forms in many application areas (such as industrial quality control, production process monitoring, security systems, traffic monitoring, inventory tracking etc.). Techniques based on various principles and sensors were developed to solve particular practical problems (ultrasound motion detection sensors, electromagnetic sensors, planar force detection sensors, computer vision systems etc.). In this paper we investigate the applicability of multielectrode capacitive sensors for monitoring the volume of interest by analyzing the disturbances in electrical field due to the influence of external objects. Capacitive sensors are particularly interesting as a low cost solution with minimum privacy issue concerns. The goal of this research was to characterize the performance of modern capacitance-to-digital converter (CDC) PicoCap PCap02 integrated circuit for detecting various types of objects in a multielectrode system configuration, with human detection as an example application. We present an analysis of an appropriate electrode geometry, propose a custom-designed data acquisition system which complies to the required capacitance measurement range and resolution, discuss sources of measurement errors and methods for minimization of their influence, and elaborate the applicability of the method beyond the simple object detection, by investigating the possibility of object class discrimination from acquired data.
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S. Tepić, P. Pejić, J. Domšić, H. Mihaldinec, H. Džapo (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
IBMS - Intelligent Building Management System Framework
The ubiquitous availability of Internet connection in residential and industrial environments enabled limitless possibilities of connecting local sensor networks using various web and cloud technologies to provide value-added services for intelligent management of building facilities. The goal of the Internet-of-Things paradigm is to enable remote access to each sensor node through the standard networking infrastructure. One of the challenges in implementing a distributed smart building management systems is to enable interoperability of many different computational platforms by providing a common protocol across the wide range of devices, with different capabilities and resources. In this paper we present an infrastructure architecture and software framework for building large interconnected sensor networks, with primary application for building management. We establish the terminology, system elements specification, functional description of different hardware and software building blocks, define thin common interoperability layer with established message semantic and event-driven framework, providing a modular architecture that is easy to adapt and extend. The communication between system components is implemented on TCP/IP stack (HTTP GET/POST requests), using JSON as a unified format for data exchange. The framework is particularly suited for implementation on low-power microcontroller-based systems on a sensor network side, and on standard web frameworks on the server side. Sensor nodes are connected through the data aggregators (which also serve as bridges between TCP/IP and sensor-specific low-level data exchange protocols) with local data acquisition cores (implementing local lightweight database storage), which communicate directly with remote scalable cloud service, designed for large sensor data collecting, syncing, storage, and event processing. System is designed for scalability, simplicity of use, interoperability, and easy extension with new types of sensor and actuators. For testing purposes, we implemented a demo system based on open source technologies that are integrated with our IBMS framework.
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M. Rožić (Mikroprojekt d.o.o., Zagreb, Croatia), M. Đonlić, T. Pribanić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
A Hybrid Local Method for Stereo Correspondence Based on Three-Dimensional Recursive Search
Obtaining dense disparity maps of stereo image pairs is a common problem in computer vision. We present a new hybrid method for dense stereo correspondence based on the well-known winner-take-all optimization and the three-dimensional recursive search (3DRS) algorithm. Originally devised for motion estimation and frame rate conversion in high definition televisions, the 3DRS algorithm employs predictive block matching to generate a coarse correspondence map between two images in a sequence. The algorithm is widely used in ASIC and FPGA implementations, achieving real-time performance in processing of 60Hz high definition video signals. In our proposed hybrid method, the 3DRS algorithm is applied to a stereo pair in order to generate a coarse disparity map, which is further optimized using a local, winner-take-all driven coarse-to-fine approach. The selected approach greatly reduces the local disparity space to be searched, yielding significantly better run-time performance while retaining or even improving the accuracy of the results. The method is evaluated using the Middlebury stereo datasets and compared with both the reference winner-take-all algorithm and coarse-to-fine hierarchical optimizations. The obtained results favor the proposed method in terms of accuracy and performance. The proposed method is suitable for implementation in custom parallel computing hardware, ASIC or FPGA.
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L. Brancik, N. Smith (Brno University of Technology, Brno, Czech Republic)
Two Approaches to Derive Approximate Formulae of NILT Method with Generalization
The paper deals with relationship between two approaches to derive approximate formulae of one specific numerical inverse Laplace transform (NILT) method, which is based on the approximation of the exp(st) function in the definition Bromwich integral, and the method based on the direct numerical integration of this ILT integral. It is shown that respective approximate formulae can also be derived by integrating the Bromwich integral numerically provided the integration path and the step are properly chosen as time-dependent. The generalization of the NILT formulae is also suggested leading to possibility to predict a limiting absolute error. The experimental error analysis is performed in the Matlab program for properly chosen Laplace transforms, and modified usage of Euler transformation to accelerate convergence of infinite series is tested successfully.
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Ž. Stojanović, S. Stojanović (Polytechnic of Zagreb, Zagreb, Croatia), I. Činikas (Vilniaus Gedimino technikos universitetas, Vilnius, Lithuania)
Laboratory Exercise for Class B/AB Power Amplifier
Laboratory exercise for amplifier class B/AB for sophomore level students is described. In first part, the influence of quiescent current and input signal amplitude on output signal waveform and amplifier efficiency is investigated. Output signal waveform is observed in time domain qualitatively and in frequency domain quantitatively. In second part, amplifier's output resistance is measured. In each measurement students have to reason out measurement results, the difference between measurement results and analytical results and measurement accuracy. Students accept concepts of quiescent point, Fourier analysis, fast Fourier transform, power, output resistance and measurement uncertainty by encompassing different areas of electrical engineering – electronics, circuit and signal analysis, power analysis and measurements.
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I. Skliarova, V. Sklyarov (University of Aveiro, Aveiro, Portugal), A. Sudnitson, M. Kruus (Tallinn University of Technology, Tallinn, Estonia)
Integration of High-Level Synthesis to the Courses on Reconfigurable Digital Systems
Digital system design constitutes an essential part of engineering education. Many universities worldwide target the respective courses to field-programmable gate arrays (FPGA) and the relevant FPGA-oriented design flow, principles and practices. Recent programmable systems-on-chip integrating a processor-based computing system and a programmable logic rely on quite a different design philosophy constituting a new challenge for future engineers. These new trends have to be certainly reflected in the pedagogical activity so that the current students would, in a few years, satisfy the growing industry requirements. In this paper we analyze the new design flow and explore in detail one particular part of it: a possibility of directly generating hardware modules from software specifications through high-level synthesis.
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Basic information:
Chairs:
Željko Butković (Croatia), Marko Koričić (Croatia), Petar Biljanović (Croatia)
Steering Committee:
Slavko Amon (Slovenia), Dubravko Babić (Croatia), Maurizio Ferrari (Italy), Mile Ivanda (Croatia), Branimir Pejčinović (United States), Tomislav Suligoj (Croatia), Aleksandar Szabo (Croatia)
International Program Committee Chairman:
Petar Biljanović (Croatia)
International Program Committee:
Alberto Abello Gamazo (Spain), Slavko Amon (Slovenia), Vesna Anđelić (Croatia), Michael E. Auer (Austria), Mirta Baranović (Croatia), Ladjel Bellatreche (France), Eugen Brenner (Austria), Andrea Budin (Croatia), Željko Butković (Croatia), Željka Car (Croatia), Matjaž Colnarič (Slovenia), Alfredo Cuzzocrea (Italy), Marina Čičin-Šain (Croatia), Marko Delimar (Croatia), Todd Eavis (Canada), Maurizio Ferrari (Italy), Bekim Fetaji (Macedonia), Tihana Galinac Grbac (Croatia), Paolo Garza (Italy), Liljana Gavrilovska (Macedonia), Matteo Golfarelli (Italy), Stjepan Golubić (Croatia), Francesco Gregoretti (Italy), Stjepan Groš (Croatia), Niko Guid (Slovenia), Yike Guo (United Kingdom), Jaak Henno (Estonia), Ladislav Hluchy (Slovakia), Vlasta Hudek (Croatia), Željko Hutinski (Croatia), Mile Ivanda (Croatia), Hannu Jaakkola (Finland), Leonardo Jelenković (Croatia), Dragan Jevtić (Croatia), Robert Jones (Switzerland), Peter Kacsuk (Hungary), Aneta Karaivanova (Bulgaria), Dragan Knežević (Croatia), Mladen Mauher (Croatia), Igor Mekjavic (Slovenia), Branko Mikac (Croatia), Veljko Milutinović (Serbia), Vladimir Mrvoš (Croatia), Jadranko F. Novak (Croatia), Jesus Pardillo (Spain), Nikola Pavešić (Slovenia), Vladimir Peršić (Croatia), Goran Radić (Croatia), Slobodan Ribarić (Croatia), Janez Rozman (Slovenia), Karolj Skala (Croatia), Ivanka Sluganović (Croatia), Vlado Sruk (Croatia), Uroš Stanič (Slovenia), Ninoslav Stojadinović (Serbia), Jadranka Šunde (Australia), Aleksandar Szabo (Croatia), Laszlo Szirmay-Kalos (Hungary), Davor Šarić (Croatia), Dina Šimunić (Croatia), Zoran Šimunić (Croatia), Dejan Škvorc (Croatia), Antonio Teixeira (Portugal), Edvard Tijan (Croatia), A Min Tjoa (Austria), Roman Trobec (Slovenia), Sergio Uran (Croatia), Tibor Vámos (Hungary), Mladen Varga (Croatia), Marijana Vidas-Bubanja (Serbia), Boris Vrdoljak (Croatia), Robert Wrembel (Poland), Damjan Zazula (Slovenia)
Registration / Fees:
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REGISTRATION / FEES
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Price in EUR
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Before May 11, 2015
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After May 11, 2015
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| Members of MIPRO and IEEE |
180
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200
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| Students (undergraduate and graduate), primary and secondary school teachers |
100
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110
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| Others |
200
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220
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Contact:
Željko Butković
Faculty of Electrical Engineering and Computing
Unska 3
HR-10000 Zagreb, Croatia
Phone: +385 1 6129 924, GSM: +385 98 951 7179
Fax: +385 1 6129 653
E-mail: zeljko.butkovic@fer.hr
Opatija - 170 years of tourism:
 Opatija – the cradle of European and Croatian tourism, a favourite destination of the aristocracy, film and music stars, artists, writers and visitors from all over the world, who come here every year to enjoy the charm of this Adriatic town – this year celebrates its 170th anniversary as a tourist resort.
This is a tradition that provides certain obligations, but is also a guarantee of quality. The reputation of a top destination that stretches back seventeen decades is today reflected in the wide range of facilities and services on offer that all together make Opatija an attractive destination for all seasons.
Opatija owes its unique image to its ideal location on the spot where the wooded slopes of Mount Učka descend all the way down to the coast, providing perfect shade along the thirteen-kilometre-long Lungomare seafront promenade. Just as the Opatija area is a meeting point of the sea and the mountain, its visual impression is a blend of different styles, as this is a melting pot where magnificent Central European elegance, playful Mediterranean charm and the historically-rich medieval architecture of the small towns in the hinterland come together.
In addition to the architecture that leaves a strong impression on every visitor, especially when the town is viewed from the sea, and its lush parks and gardens that have been Opatija's trademarks since its beginnings as a tourist resort, Opatija also has hotels and restaurants whose quality ranks alongside that of any other European destination. Opatija's gastronomic offer is based on a Mediterranean cuisine rich in fresh fish and seafood and locally grown seasonal ingredients, while the traditional recipes of this region reveal a wealth of flavours and can be sampled in the area's numerous taverns.
Opatija entered the European stage in the mid-19th century as a health resort for the European nobility, and health tourism has remained one of the main segments of the town's tourism offer right up to the present day. However, top medical experts and a wide range of spa & wellness services are just one of the reasons for visiting this town located at the top of Kvarner Bay. Also known as "the town of festivals", Opatija boasts a number of events throughout the year. The theatrical performances and concerts that take place at the magnificent Open Air Theatre are particularly impressive.
For more details please look at www.opatija.hr/ and www.opatija-tourism.hr/.
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