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inovativno promotivno partnerstvoICT u obnovljivim energetskim tehnologijama

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Program događaja
srijeda, 29.9.2021 13:30 - 15:30,
Bellavista, Grand hotel Adriatic, Opatija
1.D. Vinko, D. Bilandžija, K. Grgić, V. Mandrić-Radivojević (Faculty of electrical engineering, computing and information technology Osijek, Osijek, Croatia)
Impact and Detection of Foreign Metal Objects in Multi-User Wireless Power Transfer System 
Presence of foreign metal object in multi-user wireless power transfer (WPT) system has a negative impact on the performance of the system. In this paper we evaluate impact of foreign metal object on the performance of the WPT system. Measurements have shown that metal object placed in the magnetic field of the transmitter coil decreases the transmitter coil inductance for up to 12%. It also decreases the quality factor of the transmitter coil up to 58 %. This increases the losses in transmitter and lowers the overall efficiency of the WPT system. Eddy currents in foreign metal objects cause the increase of induced voltage on the receiver coil up to 30%. Different methods for foreign metal object detection are discussed in paper. Measurements have confirmed that proposed step response method can be used to accurately detect foreign metal objects in multi-user WPT system. The method can be used on-the-fly and can be implemented on the transmitter side without any modification on the receiver circuits.
2.F. Bogdanović, Ž. Osrečki, J. Žilak, M. Koričić, T. Suligoj (Fakultet elektrotehinke i računarstva, Zagreb, Croatia)
Comparison of Discrete Bipolar Transistors and MOSFETs for High-Speed Switching Application 
Switching performance analysis in this paper presents how Horizontal Current Bipolar Transistor (HCBT) performs under switching mode of operation compared to other market available transistor technologies, focusing mainly on power efficiency. Rudimentary measurement setup is devised, with target frequency spectrum for this analysis up to 100 MHz. Measurements were performed at frequencies of 1 MHz, 10 MHz and 100 MHz. Signal waveforms were measured at input and output of analysed device. From measured data dissipated power at each component of test circuit were calculated to determine efficiency. Obtained data shows similar performance between RF bipolar junction transistors analysed in this paper. All bipolar transistors exibit efficiency around 80% at 100 MHz, whereas the best performing MOSFET has η = 54.31%. While analysed MOSFETs show somewhat better performance at lower frequencies, but with larger performance degradation with increase in frequency. This analysis shows potential of HCBT to be used in Envelope Tracking (ET) supply power modulation and other switching techniques to obtain higher efficiencies. Most of the efficiency reduction is caused by nonideal input signal.
3.T. Markovic (imec, Leuven, Belgium), J. Bao, B. Nauwelaers (KU Leuven, Leuven, Belgium)
Interdigital Capacitor Based Microwave Heater for Continuous Microfluidics 
In this work, an interdigital capacitor (IDC) topology on Quartz substrate is employed for microwave heating at 25 GHz for picolitre volumes in continuous microfluidics (CMF). The electrodes of the IDC heater are designed using COMSOL Multiphysics to achieve rapid, contact-less and uniform heating. The CMF channel is manufactured using polydimethylsiloxane and bonded to the quartz wafer. The manufactured device is tested using simultaneous microwave excitation, temperature measurements and optical investigation. A mixture of deionized water and a fluorescent dye, Rhodamine B, is used to evaluate the heating performance of the manufactured device. A temperature increase of 20.2°C is achieved after 10 ms of heating with 1 W of power at 25 GHz.
4.F. Kostelac ( Faculty of Electrical Engineering and Computing, Zagreb, Croatia), D. Babić ( Faculty of Electrical Engineering and Computing / Eridan Communications d.o.o., Zagreb, Croatia)
Extraction of π-Capacitor Equivalent Circuit Elements for Field-Effect Transistors in Deep Pinch-off 
A heterojunction field-effect transistor in blocking (deep pinch-off) connected between two transmission lines (gate to drain) is represented as an asymmetric transmission-line gap. This configuration allows one to determine the π-capacitor equivalent network from s12(ω) or s21(ω) measurements only. We discuss the method of extracting equivalent-circuit element values and the limitations of this alternative approach to device intrinsic parameter de-embedding
5.F. Turčinović, M. Erny, V. Zoričić, N. Poletan, M. Bosiljevac (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Design of Short Range mm-wave Radar Sensing for Autonomous Object Classification 
Remote environmental and industrial sensing based on multi-spectral or radar imaging today plays an important role in ensuring sustainability and protection of natural resources, in saving time and energy in industry and agriculture, and in many other applications. Numerous examples of such systems exist which provide information like product quality to manufacturers, crops growth parameters to farmers or structural integrity details to civil engineers. With recent developments in electromagnetic millimetre-wave (mm-wave) technology and artificial intelligence implementation, short range mm-wave remote sensing is experiencing strong growth with the market dictating new applications with increasingly higher levels of system autonomy. The objective of this paper is to demonstrate methodologies and hardware that will meet the demands of these new applications by efficiently combining short range radar sensing and supervised machine learning in order to reach a high level of autonomous object classification.
6.M. Kupresak, T. Marinovic, X. Zheng, G. Vandenbosch (KU Leuven, Leuven, Belgium)
Comparative Study of Electromagnetic Field Solvers for the Modeling of Nanoscale Plasmonic Scatterers 
The nanoscale systems are of great importance in modern science and technology, offering a wide range of possible daily life applications. In order to characterize the electromagnetic (EM) properties of metallic nanotopologies, the commercialized computational tools COMSOL, CST, and Lumerical have been widely used. In this work, the performance of the above tools is compared, through the investigation of the plane wave response of canonical spherical and cubical nanoparticles. It is demonstrated that not all EM field solvers provide an accurate description of the nanoparticle’s behavior.
četvrtak, 30.9.2021 9:00 - 13:00,
Bellavista, Grand hotel Adriatic, Opatija
Device Physics 
1.L. Marković, T. Knežević (University of Zagreb, Faculty of Electrical Engineering and Computing, Micro and Nano Electronics La, Zagreb, Croatia), L. Nanver (University of Twente, Faculty of Electrical Engineering Mathematics and Computer Science, Enschede, Netherlands), T. Suligoj (University of Zagreb, Faculty of Electrical Engineering and Computing, Micro and Nano Electronics La, Zagreb, Croatia)
Modeling of Electrical Properties of Ge-on-Si Diode with Nanometer-thin PureGaB Layer 
Deposition of a nanometer-thin layer-stack of pure gallium and boron (PureGaB) on arsenic (As)-doped epitaxial germanium (Ge) forms a shallow-junction photodiode, reported to have almost ideal I-V characteristics, low saturation current densities, and high responsivity down to 255 nm wavelengths. In this work, different physical mechanisms that could explain the high anode Gummel number in PureGaB-Ge-on-Si diode have been examined. A model for point-defect-mediated diffusion of B and Ga in Ge has been developed. Formation of a shallow pn junction has been modeled using 1D process simulations of B and/or Ga drive-in from the PureGaB layer. B diffusion resulted in junction depths less than a nanometer deep, while Ga formed a highly doped p+ regions with peak concentrations >1020 cm-3 and junction depths from 31 nm to 123 nm, depending on the applied sets of diffusion parameter. Both approaches have been used to fit the I-V characteristics of a fabricated PureGaB Ge on Si diode: B-only diffusion model with negative interface charge concentration of 1.9·1013 cm-2 for suppression of electron injection and Ga diffusion model, self-sufficient for the explanation of low electron current densities. Both proposed models give possibilities to obtain a Gummel number of ≈ 21014 s/cm4, matching the value extracted from I-V characteristics of a fabricated device.
2.D. Schwarz, S. Schäfer, L. Seidel, H. Funk, D. Weißhaupt, M. Oehme (University of Stuttgart, Institute of Semiconductor Engineering, Stuttgart, Germany), V. Schlykow, Jülich, Germany), V. Kiyek, Jülich, Germany), D. Buca (Forschungszentrum Jülich, Peter Grünberg Institute (PGI-9), Jülich, Germany), J. Schulze (University of Stuttgart, Institute of Semiconductor Engineering, Stuttgart, Germany)
MBE-grown Ge0.92Sn0.08 Diode on RPCVD-grown Partially Relaxed Virtual Ge0.92Sn0.08 Substrate 
The binary alloy semiconductor Ge1-xSnx is a promising candidate for the monolithic integration of optoelectronic circuits on Si due to its reported direct bandgap at specific Sn concentration and strain. However, while the directness of Ge1-xSnx improves with increasing Sn concentration, compressive strain counteracts with this trend. Since too high Sn concentrations lead to high amount of crystal defects due to Sn segregation, the growth of strain relaxed Ge1-xSnx would allow a decreasing Sn concentration and therefore an increasing crystal quality at once. The key issue is the growth of strain relaxed virtual Ge1-xSnx substrates for the subsequent epitaxy of Ge1-xSnx device structures, which seems to be the biggest obstacle with molecular beam epitaxy (MBE) so far. In this work, we report the epitaxy of partially relaxed Ge0.92Sn0.08 layers via reduced pressure chemical vapor deposition (RPCVD), which serve as virtual substrate for the consecutive MBE of Ge0.92Sn0.08 diode structures. This consecutive epitaxy process requires an extensive surface cleaning sequence, which had to be developed first. The quality of the grown diode structures was verified using X-ray diffraction (XRD). Furthermore, diodes were fabricated and electrically characterized. We will show that our approach is promising for high qualitative Ge1-xSnx devices on Si.
3.L. Seidel, D. Schwarz, M. Oehme, A. Causevic, H. Funk, D. Weisshaupt, F. Berkmann, J. Schulze (Institute of Semiconductor Engineering, Stuttgart, Germany)
Electrical Characterization of SiGeSn/Ge/GeSn-pin-Heterodiodes at Low Temperatures 
The combination of the ternary alloy Si1-x-yGexSny with Ge1-xSnx is very promising for electrooptical applications in the near infrared regime up to 2.5 µm wavelength. With the tunable bandgap at a non-varying lattice constant Si1-x-yGexSny is predestined for the lattice matched growth on a Ge virtual substrate and the integration of pseudomorph Ge1-xSnx layers with high Sn content (> 10 %). The main challenge of the growth of such alloys is to achieve a low density of defects. However, in the last few years there was a major progress in growing highly doped Si1-x-yGexSny layers with good crystal quality. In this work we investigate the electrical characteristics of Si1-x-yGexSny/Ge/Ge1-xSnx-pin-heterodiodes in a temperature range from 300 K to 8 K. This temperature depended measurement provides the opportunity for a more precise characterization of such diodes. A linear relation between reciprocal temperature and the ideality factor is found. With the extrapolation of this relation up to room temperature the ideality factor of the diode is calculated (η=1.22). From the temperature dependent reverse current the mean activation energy of the defects is determined (E_A=-0.178 eV). We discuss the possibility to utilize such diodes for near infrared sensor applications.
4.N. Lovecchio, D. Caputo, V. Ferrara, G. de Cesare (Sapienza University of Rome, Rome, Italy)
On-Glass Thin Film Transistor Based on p-i-n Amorphous Silicon Junction 
Amorphous silicon (a-Si:H) thin film transistor (TFT) based on metal/oxide/semiconductor structure (MOS) are widely employed in active matrix display as switching element. Compared to crystalline field effect transistor (MOSFET), a-Si:H device present a very high ON/OFF current ratio (in the range of 107) with OFF current in the range of 10-11A. However, these kind of devices is not used for analog application due to their low channel conductance. Furthermore, in order to achieve good performances an oxide layer grown at temperatures above 250°C is required. In this work we present a Junction Field Effect Transistor (JFET) based on a-Si:H. The stacked structure of the device, deposited on glass substrate, is: metal gate/p-doped/intrinsic/n-doped/drain-source metal contacts. The a-Si:H layers are deposited by Plasma Enhanced Chemical Vapor Deposition at around 200 °C. The drain-source channel is the n-doped layer and its resistance is modulated by the negative voltage applied to the gate (VG). The width of the depletion region inside the lightly doped n layer increases with the absolute value VG. The higher conductance is achieved for VG=0. At VG <= Vp (threshold voltage) the n region is completely depleted, and the current device is close to zero. In order to have high transconductance and straightforward modulation, high dopant concentration in the n-doped layer is required. However, in a-Si:H material high doping induces high defect density which hinders the depletion of the doped layers. Therefore a crucial fabrication parameter of the JFET is the n-doping concentration as well as its thickness. Other important parameters are thickness and quality of intrinsic layer. Indeed, this region has to sustain the electric field at the junction and to present a low defect density in order to make the depletion of the n-layer more easy. Based on these considerations, we fabricated several JFET structures, with W/L = 10, achieving Vp around -2 Volt and transconductance values in the order of 10-7 A/V at VGS=0. These results make the device suitable for applications in linear circuit and, thanks to their low deposition temperature (around 200 °C) extremely attractive for process on flexible substrates.
5.H. Funk, D. Weisshaupt, D. Schwarz (Institute of Semiconductor Engineering, Stuttgart, Germany), D. Bloos, J. van Slageren (Institute of Physical Chemistry, Stuttgart, Germany), J. Schulze (Institute of Semiconductor Engineering, Stuttgart, Germany)
Characterization of Fe Micromagnets for Semiconductor Spintronics by In-Field Magnetic Force Microscopy 
Recent developments in quantum electronics, particularly spin-qubit systems and semiconductor spintronics, provide new applications for micromagnets. The stray field of properly placed micromagnets can be employed to manipulate spin-qubits using rf-signals. Micromagnets are used as the injector and detector contacts in semiconductor spintronics. For both applications, singledomain magnets with precisely known magnetic properties, with and without external field, are required. We report on Fe micromagnets with different aspect ratio, fabricated using standard semiconductor processing technology. We describe a simple setup using a custom-built electromagnet and conventional atomic force microscope to characterize the micromagnets in an external magnetic field using magnetic force microscopy (MFM). We use this setup to characterize the fabricated micromagnets’ domain structure and switching behaviour. We show that MFM, together with the custom-built electromagnet is a simple, yet versatile method to characterize micromagnets for applications in quantum electronics. We furthermore show that the fabricated micromagnets all exhibit the desired singledomain state. The micromagnets differ in their coercive field, depending on the aspect ratio. This makes these micromagnets suitable for spin-injection and spin-detection.
6.F. Berkmann, Stuttgart, Germany), M. Ayasse (University of Stuttgart, Institute for Semiconductor Engineering (IHT), Stuttgart, Germany), F. Mörz (University of Stuttgart, 4th Physics Institute , Stuttgart, Germany), I. Fischer (Brandenburg University of Technology, Experimental Physics and Functional Materials, Cottbus, Germany), J. Schulze (University of Stuttgart, Institute for Semiconductor Engineering (IHT), Stuttgart, Germany)
Titanium and Nickel as alternative materials for mid Infrared Plasmonics 
Finding suitable materials with low Drude losses for plasmonic applications at mid-infrared wavelengths is challenging. Highly doped Germanium and Germanium Tin alloys have been investigated to that end but are difficult to utilize at wavelengths closer to the near infrared region. In this work, we present results on the fabrication and optical characterization of Titanium and Nickel comb antennas. Extinction spectra were obtained via Fourier Transform Infrared (FTIR) Spectroscopy and verified via Finite Difference Time Domain (FDTD) simulation. The measured spectra show distinct extinction peaks in the range between 4 μm and 11 μm, which can be correlated to a plasmonic mode forming at the antenna substrate interface showing that it is possible to excite localized plasmonic modes at the interface between such antennas and a Silicon substrate.
7.E. Sigle, Stuttgart, Germany), D. Weißhaupt, Stuttgart, Germany), M. Oehme, Stuttgart, Germany), H. Funk, Stuttgart, Germany), D. Schwarz, Stuttgart, Germany), F. Berkmann, Stuttgart, Germany), J. Schulze (Universität Stuttgart, Institut für Halbleitertechnik (IHT), Stuttgart, Germany)
Strained Ge Channels with High Hole Mobility Grown on Si Substrates by Molecular Beam Epitaxy 
Strained Modulation-doped quantum wells (QW) offer a huge potential for semiconductor device application due to their high mobility. The material Ge is particularly interesting here, exhibiting the highest bulk hole-mobility of all known semiconductors. However, the growth for Ge-QW structures is quite complex and a special virtual substrate (VS) technique is needed. The VS is commonly grown with thicknesses of over 1 µm, making it difficult for integration with other devices on a single chip. In this paper, we report on the growth of a 15 nm thick strained Ge-QW on top of a 200 nm thick Si0.2Ge0.8 VS. The VS is grown by deposition of 100 nm Ge followed by a high temperature annealing step, and a 100 nm thick Si0.2Ge0.8 buffer using Molecular Beam Epitaxy. The resulting two-dimensional hole gas reaches a hole mobility of over 8⋅104 cm2 V-1 s-1 with a corresponding sheet carrier density of 5.7⋅1011 cm-2 at 8 K. The Ge-QW is further analysed, and comparing it to a sample with a higher VS thickness, a possible limitation of the mobility due to background doping is being discussed. These results show that CMOS compatible device integration of the Ge-QW is possible, thin buffer layers suffice for the mobilities achieved and background doping limits the low temperature mobility.
8.D. Weißhaupt, Stuttgart, Germany), H. Funk (Institute of Semiconductor Engineering (IHT), Stuttgart, Germany), C. Sürgers, Karlsruhe, Germany), G. Fischer (Physikalisches Institut (PHI), Karlsruhe, Germany), M. Oehme, Stuttgart, Germany), D. Schwarz (Institute of Semiconductor Engineering (IHT), Stuttgart, Germany), I. Fischer (Experimental Physics and Functional Materials, Cottbus, Germany), J. van Slageren (Institute of Physical Chemistry (IPC), Stuttgart, Germany), J. Schulze (Institute of Semiconductor Engineering (IHT), Stuttgart, Germany)
Formation of Mn5Ge3 on a Recess-Etched Ge (111) Quantum-Well Structure for Semiconductor Spintronics 
Ge two-dimensional hole gases (2DHG) formed in strained, modulation-doped quantum-wells are highly suitable for future spintronic applications due to their good transport properties. For electrical spin-injection into a Ge 2DHG, the ferromagnetic alloy Mn5Ge3 can be used as a contact material. The Mn5Ge3 grows as interlayer by interdiffusion between an evaporated Mn layer and the Ge 2DHG. To fulfil the magnetic requirements, the Mn5Ge3 contact must not contain Si and should be thinner than 20 nm. Since the Ge 2DHG is capped with Si20Ge80, it must be removed before contact alloying. In this paper, we report on the growth of a ferromagnetic Mn5Ge3 thin film directly on the strained Ge. The Si20Ge80 capping layer was removed using Ar milling. We report the magnetic properties of the grown Mn5Ge3 on a Ge (111) 2DHG, analysed by superconducting quantum interference device magnetometry and compare the results to an unetched Mn5Ge3 on Ge (111) reference. Furthermore, temperature-dependent Hall measurements using the Mn5Ge3 contacts on the Ge (111) 2DHG confirm the electrical contact to the high mobility 2DHG. These results are an important step on the way for an electrical spin-injection into a Ge 2DHG which is a promising material for future spintronic applications.
9.I. Berdalović, M. Poljak, T. Suligoj (Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia)
Modelling of Electrostatics and Transport in GaNBased HEMTs under Non-Equilibrium Conditions 
High electron mobility transistors (HEMTs) consisting of GaN and its alloys, most commonly AlGaN, have been gaining popularity as the next generation of high-speed devices for radiofrequency and power applications. Although a high concentration of 2D electrons in such structures can be obtained even in equilibrium, i.e. with a zero gate bias, in recent years there has been a tendency of developing normally-off, i.e. enhancement-mode GaN HEMTs to ease integration with the associated gate-driver circuitry. Therefore, accurate simulation of key electrical properties of these devices, such as electron mobility, becomes important even in non-equilibrium conditions, i.e. with an applied gate bias. This paper describes a simulation framework designed to enable the modelling of 2DEG mobility in enhancement-mode HEMTs. Apart from the Schrödinger and Poisson equations which need to be solved for the equilibrium case, the current continuity equations for electrons and holes also need to be satisfied when a positive gate bias is applied. All these equations are solved in a self-consistent numerical procedure to obtain a correct solution of the electrostatic problem for an arbitrary gate bias, as well as the discrete states and carrier wavefunctions needed for semi-classical mobility calculations. The procedure is demonstrated by simulating an advanced enhancement-mode device with a p-GaN cap and comparing the calculated electron concentrations and mobilities with available experimental results.
10.M. Bendra, J. Ender, S. Fiorentini, T. Hadamek (Christian Doppler Laboratory for NovoMemLog at the Institute for Microelectronics TU Wien, Vienna, Austria), R. Orio (Institute for Microelectronics TU Wien, Vienna, Austria), V. Sverdlov (Christian Doppler Laboratory for NovoMemLog at the Institute for Microelectronics TU Wien, Vienna, Austria), W. Goes (Silvaco Europe Ltd, Cambridge, United Kingdom), S. Selberherr (Institute for Microelectronics TU Wien, Vienna, Austria)
Finite Element Method Approach to MRAM Modelling 
Spin-transfer torque magnetoresistive memory (STT-MRAM) is among the most promising candidates for emerging memories. Thus, reliable simulation tools provide an important aid for understanding and improving the design of such devices. In this work, we are concerned with the simulation of STT-MRAM. The well-known Landau-Lifschitz-Gilbert (LLG) equation describes the magnetization dynamics. Since we are dealing with STT-MRAM, an additional torque term must be added to the LLG equation. The torque acting on the magnetization is generated by the non-equilibrium spin accumulation due to the electric current flowing through the structure. The partial differential LLG equation with the additional torque computed from the spin accumulation is solved using the finite element method (FEM). We implemented several time integration schemes using an open source FEM library. In order to verify and compare the FEM implementation, the simpler finite difference method (FDM) is used as a reference. By calibrating and increasing the time step size it is possible to achieve an almost identical switching behavior as with FDM. The proper calibration and verification is essential to proceed to the next stage which is to simulate a more realistic multilayer structure with a composite switching layer consisting of ferromagnetic layers separated by nonmagnetic buffers.
11.M. Poljak, M. Matić ( Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
DFT-Based Tight-Binding Model for Atomistic Simulations of Phosphorene Nanoribbons 
We report a set of tight-binding Slater-Koster parameters calibrated on ab initio density functional theory (DFT) bandstructure calculations for monolayer black phosphorus or phosphorene, which is among the most promising 2D materials for future nanoelectronic applications. The bandstructure is calibrated so that both the conduction and valence bands are accurately reproduced in the energy range of interest, which allows the analysis of both electron and hole transport properties. The new DFT-TB model is assessed by performing quantum transport (Green’s function formalism) calculations of density of states, quantum transmission and conductance, for pristine phosphorene nanoribbons of various widths, and the results are compared to calculations done using a TB model from the literature. We find that the new DFT-TB model results in higher transmission, conductance, and density of states, and that it accurately reproduces the asymmetry between electron and hole electronic and transport properties observed in reported DFT results.
12.M. Matić, M. Leljak, M. Poljak ( Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Estimating OFF-state Leakage in Silicene Nanoribbon MOSFETs from Complex Bandstructure 
We study the OFF-state leakage current in silicene nanoribbon (SiNR) MOSFETs using atomistic tight-binding Hamiltonians. Complex band structure is computed for these devices and the energy-dependent tunneling attenuation is analyzed. We investigate both the tunneling and thermionic components of the OFF-state leakage for SiNR MOSFETs with channel lengths under 15 nm, using under-the-barrier and top-of-the-barrier models. The current components and attenuation are investigated for various nanoribbon widths and lengths. We report a limited design space where SiNR dimensions provide acceptable OFF-state leakage according to the goals set by the International Roadmap for Devices and Systems (IRDS).
četvrtak, 30.9.2021 15:00 - 19:00,
Bellavista, Grand hotel Adriatic, Opatija
1.J. Mikulic, G. Schatzberger (ams AG, Premstaetten, Austria), A. Baric (FER, Zagreb, Croatia)
Self-Referenced 32-kHz Rotating Capacitor Relaxation Oscillator with Chopped Comparator Offset-Voltage Cancellation 
This work presents a novel relaxation oscillator architecture using a rotating capacitor integrator and a chopped comparator. The oscillator is self-referenced, using the resistor instead of the current source, together with the reference voltage realized with the resistor divider connected to the supply voltage. The oscillator prototype is designed and manufactured in 180 nm technology, typically consumes 1.5 µA at 32 kHz, has a frequency variation of +-0.44% in the temperature range from -40 to 105°C and +-0.3% in the power supply range from 1.62 to 1.98 V. The oscillator has a start-up time of 15.4 µs and is operational in the low supply voltage range.
2.K. Špoljarić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia), J. Mikulić (ams AG, Premstaetten, Austria), A. Barić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Design and Testing of an 8-Bit Current DAC in 180-nm CMOS Technology 
This paper presents an 8-bit current DAC in 180-nm CMOS technology. The circuit is designed and simulated in Cadence Virtuoso software and then processed and measured. The measurement results are presented in this paper and compared to simulation results. The 8-bit current DAC can be used to compensate variations in the parameters of circuit components caused by production. The simulation and measurement results of the differential and integral nonlinearities for each input code of the digital to analog converter in all operating conditions are presented.
3.A. Traživuk (Faculty of Electrical Engineering, Zagreb, Croatia), A. Alberts (Sydelity, Kruisem, Belgium), A. Barić, V. Čeperić (Faculty of Electrical Engineering, Zagreb, Croatia)
Decoupling Analog Conservative Connections Using Waveform Relaxation Method 
This paper presents a method for decoupling analog conservative connections suitable for implementation in SPICE simulators for simulation of large electronic systems. The Waveform relaxation method relies on insertion of interfaces between sub-circuits of the system, mimicking the behavior of transmission lines in a way that they do not change the overall response of the system. This results in a possibility to split large systems into smaller sub-systems and to calculate the response of each of them in isolation and through several iterations, thus reducing the total simulation time.
4.T. Fogec, J. Bačmaga, I. Krois, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Characterization of GaN-Based Synchronous Buck Converter Operating in MHz-Range 
A discrete synchronous buck converter based on a GaN half-bridge power stage is designed and characterized. The operation of the designed converter is analyzed for different input voltages, load currents, switching frequencies and duty cycles. Depending on the operating condition of the converter, power efficiencies up to 98% can be achieved. Two different topologies of the input capacitive network are designed to analyze their impact on the conducted electromagnetic noise generated by the converter operation. The placement of the input decoupling capacitors on both sides of the two-layer board minimizes the loop inductance of the return current path and reduces the generated conducted noise.
5.D. Arbet, M. Potočný, M. Kováč, V. Stopjaková (Faculty of Electrical Engineering and Information Technology, Bratislava, Slovakia)
Fully On-Chip Low-Drop Regulator for Low-Power Applications 
The paper is focused on the design and analysis of a fully on-chip Low-Drop Regulator (LDO) that was fabricated in 130 nm CMOS technology. The proposed LDO was designed using the low-voltage technique in order to achieve reliably work in the wide input voltage range. The output voltage of the proposed LDO was set to 0.4 V while the maximum input voltage can be 1.2 V. The achieved results shows high efficiency regulation and high conversion efficiency under minimal supply voltage conditions. The presented LDO has been used in complex ultra-low voltage systems that is fully integrated on chip.
6.I. Skeledžija (Fakultet elektrotehnike i računarstva, Zagreb, Croatia), J. Mikulić (ams AG, Premstätten, Austria), A. Barić ( Fakultet elektrotehnike i računarstva, Zagreb, Croatia)
200-MHz and 400-MHz Self-Biased Temperature-Compensated Ring Oscillators in 180-nm CMOS Technology 
Conventional ring oscillators are inherently prone to output frequency variation with the change of temperature and supply voltage. Various current starving techniques are used to control the current through the inverter delay stages in order to stabilize the output frequency. A simple current starved design with current mirrors and a PTAT bias generator can achieve a total accuracy in the order of 10% across the temperature range from -40°C to 125°C. This paper presents a ring oscillator architecture with an improved biasing circuit, which improves the total accuracy of the output frequency to around 1% in the same temperature range. To achieve this result, the design uses a self-biasing scheme in combination with five differential output inverter delay stages. No additional circuitry is required for the manipulation of the control voltage. 200-MHz and 400-MHz variants of the oscillator are presented, each with two different implementations of the power down mode. This makes for a total of four different oscillator cores designed in 180-nm CMOS technology. The performance of the manufactured oscillators is evaluated, and measurement results are compared with simulations.
7.F. Kostelac, A. Ćoza, D. Jurišić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Fractional-Order Elements Using Tunable OTA-C Structures 
Most of the research on fractional-order (FO) systems has been presented for passive realization of FO capacitors and inductors. In this paper, an active realization of a FO capacitor or a constant-phase element (CPE) is presented in the form which can be realized as an integrated circuit. The realization is demonstrated using OTA-C structures in AMS 0.35um C35B4 technology. We propose the realization of active constant phase elements using OTAs having MOS transistors in the saturation region. The linearization of each OTA is applied by source degeneration. We use standard approximation such as second-order continuous fraction expansion (CFE) to design three non-integer orders of 1/3, 1/2 and 2/3. We propose tuning method using different bias currents of OTAs to obtain desired phase characteristics of the CPE.
8.A. Zeljko, I. Prevarić, M. Poljak (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Simulation Analysis of XOR Gates Implemented with a Memristor-Based Neural Network 
We design and analyze a neuromorphic circuit that operates as a neural network and behaves as XOR logic gates. Artificial neurons are represented with operation amplifiers while weighted connections are realized with memristors. Generalized Verilog-A model is employed for memristor circuit simulations, which is calibrated on experimental data. We demonstrate control voltages used to read/write memristors and analyze its resistance levels and range. Additionally, power consumption simulation and Monte Carlo analysis are made to characterize XOR circuit dissipation and robustness to device-to-device variability, respectively.
petak, 1.10.2021 9:00 - 13:00,
Bellavista, Grand hotel Adriatic, Opatija
Systems and Signal Processing 
1.I. Rep, D. Špikić, D. Vasić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Eddy Current Inversion of Lift-off, Conductivity and Permeability Relaxation 
We use a stochastic inversion of multi-frequency eddy current data for determination of the lift-off, conductivity and permeability of a plate made of magnetic and electrically conductive material. We use a simplified Debye relaxation relation to model the frequency dependent magnetic permeability. The inverted results are posterior probability densities of the plate parameters. The approach is verified using the synthetic data from the impedance model of a coil above a magnetic plate at three excitation frequencies.
2.Z. Šverko (University of Rijeka – Faculty of Engineering/Department of Automatics and Electronics, Rijeka, Croatia), J. Sajovic (University Medical Centre, Ljubljana, Slovenia), G. Drevenšek (University of Ljubljana – Faculty of Medicine & University of Primorska – Faculty of Mathematics, Na, Ljubljana; Koper, Slovenia), S. Vlahinić (University of Rijeka – Faculty of Engineering/Department of Automatics and Electronics, Rijeka, Croatia), P. Rogelj (University of Primorska – Faculty of Mathematics, Natural Sciences and Information Technologies, Koper, Slovenia)
Generation of Oscillatory Synthetic Signal Simulating Brain Network Dynamics 
In this paper, generation of oscillatory synthetic signal simulating brain network dynamics is proposed. The methods follows the expectations of brain network connectivity, which include expressed phase angle differences and signal mixture. We have generated thirty-two signals simulating two groups of sixteen electrodes. Each signal is a mixture of two signal components. The first signal component is synchronized within a group of electrodes but delayed to obtain different phase angles, while the second signal component is unique to each electrode. This simulation give us possibility to present that all brain regions or sources are not connected with each other and that the phase difference between connected oscillators (sources or channels) is not necessary close to zero and could be arbitrary. Phase locking value (PLV) and phase lag index (PLI) measures of connectivity have been calculated on the synthetic signals.
3.A. Serov, A. Shatokhin, N. Serov (National Research University “Moscow Power Engineering Institute”, Moscow, Russian Federation)
Application of the Signal Samples Approximation for Accurate RMS Measurement 
Nowadays the root-mean-square (RMS) is one of the most informative parameters of electrical power network signals. By definition, the RMS measurement technique involves averaging the square of the input signal over a multiple of the input signal period. However, for digital measurement methods, the input signal is represented as a sequence of discrete samples obtained by applying analog-to-digital converter (ADC). The paper discusses ways of approximating of the signal samples by applying polynomial functions of zero, first and second order. Analytical expressions are obtained for the RMS measurement error for the case of applying approximation polynomials of different order. The influence of the input signal amplitude, signal frequency, initial phase, sampling frequency and total measurement time on the RMS measurement error for the case of applying these measurement methods is considered. Particular attention is paid to the influence of the input signal frequency deviation on the RMS measurement error. Methods for reducing the measurement error for the case of sinusoidal and polyharmonic input signals are proposed. By application of Matlab and Simulink software packages, a model of simulation mathematical modeling for all considered approaches is performed.
4.J. Kundrata, D. Tomić, I. Maretić, A. Barić (University of Zagreb Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Particle filter implemented as a hardware accelerator in Cortex-M core periphery 
Particle filters are a group of filtering methods based on recursive Bayesian filters which can be used to estimate the state of an observed dynamical system. The main advantage of the particle filters when compared to other similar filtering methods is that it can handle a nonlinear system which includes non-Gaussian noise sources. A hardware accelerator represents a digital module which is specifically made to perform some function. The module is adapted exclusively to the designed function which the module executes more efficiently and faster than it is possible using a software implementation on a general-purpose processing core. This paper analyses a hardware accelerator which implements a particle filter used in the inertial measurement unit (IMU) measurements. The accelerator is used in periphery of a low power and low gate count Cortex-M0 core. The accelerator is evaluated w.r.t. the power, performance and area (PPA) and it is compared to a software implementation of an equivalent particle filter executed on the Cortex-M core.
5.R. Babojelić, Š. Ileš, J. Matuško (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Robust Set-Based Predictive Control for Grid-Tied Inverter with LCL Filter 
This paper presents a robust set-based model predictive current control algorithm for grid-tied inverter with an LCL filter. Taken into consideration are variations in grid frequency and grid impedance, as well as uncertainties in the LCL filter parameters which are modeled in polytopic linear parameter varying framework. A robust state feedback gain based on $H_{\inf}$ and regional pole placement constraints is synthesized solving a linear matrix inequality (LMI) problem, using this gain robust positively invariant terminal set is computed. From the terminal set, a family of control invariant sets is computed offline. Optimization problem is solved online subject to invariant sets membership constraint steering the states of the system to terminal set in finite time. Control algorithm is tested in simulation under grid frequency disturbance and various power loads.
6.M. Golubić, J. Kundrata, A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia)
Verification of the Legacy Compatibility of the MIPI I3C Master 
For decades now, an I2C technology has been an industry proven communication protocol in mobile and stationary devices. As the industry advances and the number of peripheral devices and data speeds rise, new protocols are being developed and implemented. The I3C is a backward-compatible successor to the I2C and achieves multiple gains in: speed, operations and energy efficiency. A test method is developed to verify I3C Master parameters. The method can evaluate both, the new I3C and legacy (I2C) signal parameters. The approach to the latter is presented in this paper.
7.T. Đuran, B. Komljen, V. Šimović (Zagreb University of Applied Sciences, Zagreb, Croatia)
Comparison of different methods for efficiency determination IEC for specific induction motor 
As energy efficiency is becoming more and more important, it was no surprise that IEC introduced new standards with mandatory efficiency classes for the biggest electric power consumers, electric motors. More precisely, induction motors which are estimated to use more than 60% of worldwide electric energy. IEC 60034-30-1:2014 defines efficiency classes IE1, IE2, IE3 and IE4 (where IE4 is highest rating i.e. biggest energy savings) for induction motors rated for sinusoidal voltage. Measurement methods, required equipment and data analysis are described in 60034-2-1. Edition 2.0 of this standard came into force in June 2014 and replaced edition 1.0. from year 2007. Before this standard, the valid standard was IEC 60034-2:1996. The main issues are: efficiency classes became mandatory from year 2009 and not just voluntary as before, an agenda to unify class standards all over the world under these new IEC standards has been put forth and measurement methods are standardized worldwide. In this paper, one induction motor will be tested according to the newest standard and analyzed to check how three different methods of loss calculation affect efficiency. Loss calculation will be determined acc. to IEC 60034-2, IEC 60034-2-1 (direct and indirect method).

Osnovni podaci:

Marko Koričić (Croatia), Željko Butković (Croatia)


Slavko Amon (Slovenia), Dubravko Babic (Croatia), Maurizio Ferrari (Italy), Mile Ivanda (Croatia), Branimir Pejčinović (United States), Mirko Poljak (Croatia), Jörg Schulze (Germany), Tomislav Suligoj (Croatia), Aleksandar Szabo (Croatia), Davor Vinko (Croatia)

Do 13.9.2021.
Od 14.9.2021.
Članovi MIPRO i IEEE
Studenti (preddiplomski i diplomski studij) te nastavnici osnovnih i srednjih škola

Popust se ne odnosi na studente doktorskog studija.


Marko Koričić
Fakultet elektrotehnike i računarstva
Unska 3
10000 Zagreb, Hrvatska

Tel.: +385 1 6129 671
GSM: +385 98 671 391
Fax: +385 1 6129 653

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Mjesto održavanja:

Opatija, sa 170 godina dugom turističkom tradicijom, vodeće je ljetovalište na istočnoj strani Jadrana i jedno od najpoznatijih na Mediteranu. Ovaj grad aristokratske arhitekture i stila već 170 godina privlači svjetski poznate umjetnike, političare, kraljeve, znanstvenike, sportaše, ali i poslovne ljude, bankare, menadžere i sve kojima Opatija nudi svoje brojne sadržaje. 

Opatija svojim gostima nudi brojne komforne hotele, odlične restorane, zabavne sadržaje, umjetničke festivale, vrhunske koncerte ozbiljne i zabavne glazbe, uređene plaže i brojne bazene i sve što je potrebno za ugodan boravak gostiju različitih afiniteta. 

U novije doba Opatija je jedan od najpoznatijih kongresnih gradova na Mediteranu, posebno prepoznatljiva po međunarodnim ICT skupovima MIPRO koji se u njoj održavaju od 1979. godine i koji redovito okupljaju preko tisuću sudionika iz četrdesetak zemalja. Ovi skupovi Opatiju promoviraju u nezaobilazan tehnološki, poslovni, obrazovni i znanstveni centar jugoistočne Europe i Europske unije općenito.

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