Event program

Wednesday, 5/28/2014 3:00 PM - 7:00 PM, Bellavista, Grand hotel Adriatic, Opatija Chair: Dubravko Babić (Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia)   Invited Paper  J. Turković (CEI Mikroelektronika d.o.o., Zagreb, Croatia) Nanotechnology, from the Recent History to (Un)Predictable Future  The diversity of nano-themes (nano science, nanoelectronics, nano materials, and other nano-something), did not result in sharper focus on the substantial processes behind the all of it. The author suggests that nanotechnology originated from the methods of microelectronics from the late1980's: ever growing complexity of mixed CMOS and bipolar planar silicon technology, and concept of MEMS devices as a way of integrating functions (and thinking) from former mutually exclusive area of electronics, machine engineering, biology, chemistry etc. The fully developed diagnostic methods enabled deep and accurate insights into the structure of material, and the methods of producing thin layered structures produce new complex entities with exotic physical and/or chemical properties. What is the impact of nanotechnology on the world outside the usual scientific community, from something like small business to corporative imperial giants? The author presents two examples of nano structured products: substrates for TEM and new type of MOS cell based on graphene and silicon as very appropriate cases for the business environment. Nanotechnology without any doubt can give complex structures with enlarged computing and processing power in very near future. But, what is it all about? Do we really need a smart toilet bowl, wich processes Tbyte information to make our stay in such a place more meaningful? In other words, do we need such an intense development just to produce new gadgets? From commercial point of view, the answer is a big YES. From the point of view of global human society progress, the answer is no. The rest of the paper presents the concept of the anisotropic boundaries as a product of already reached state of the nanotechnology, what boundaries can change the global civilizational paradigm, turning the meaning of the nano-something from the gadgetry to a new chapter in the evolution of human society. Regular Papers  1. V. Mitsa, R. Holomb (Institute of Solid State Physics and Chemistry, Uzhhorod, Ukraine), G. Lovas ( Institute of Solid State Physics and Chemistry, Uzhhorod, Ukraine), M. Veres (Research Institute for Solid State Physics and Optics, Budapest, Hungary), M. Ivanda (Rudjer Boskovic Institute, Zagreb, Croatia), T. Kovach (Institute of Solid State Physics and Chemistry, Uzhhorod, Ukraine) Spectroscopic Evidence of Coexistence of Clusters Based on Low (α) and High Temperature (β) GeS2 Crystalline Phases in Glassy Germanium Disulfide Matrix  Technologically modified g-GeS2(TiVj) glasses prepared by melt quenching from different temperatures (Ti) and with different cooling rates (Vj) were studied using Raman spectroscopy and model calculations. Differential Raman spectra {IRGeS2(TiV1)-IRGeS2(T2V1)} showed the splitting of the main, most intensive wide-band, centered at 340 cm-1. The position of the peaks found in the differential Raman spectra near 340 and 360 сm-1 and position of the main vibrational modes in the ordinary Raman spectra of low- and high-temperature crystalline phases (α-, β-GeS2) were found to be in good agreement. Vibrational spectra of 4- and 6-member ring fragments selected from crystalline structure of β-GeS2 were also determined using model calculations. Based on rings composed of GeS4 tetrahedrons connected by corners and edges the structural interpretation of the vibrational bands of g-GeS2(TiVj) at 360, 370 and 433 сm-1 in their Raman spectra was performed. The existence of homopolar Ge-Ge and S-S “defect” bonds in the structure of germanium disulfide glasses was proved by formation of 5-member rings. Formation of fragments of both low- and high-temperature α-, β-GeS2 crystalline phases in the structure of g-GeS2(TiVj) glasses indicates the existence of mixed medium-range ordering in g-GeS2. 2. L. Mikac, M. Ivanda, M. Gotić, T. Mihelj (IRB, Zagreb, Croatia) Synthesis and Characterization of Silver Colloidal Nanoparticles and Their Application in Surface Enhanced Raman Spectroscopy  Silver colloids were produced by chemical reduction of silver salt (silver nitrate, AgNO3) solution. As a reducing agents trisodium citrate, sodium borohydride, ascorbic acid, PVP and glucose were used. The characters of silver nanoparticles were investigated using UV-Vis spectrophotometer, dynamic light scattering (DLS), zeta (ζ) potential measurements and scanning electron microscopy. The as prepared silver nanoparticles were used in SERS measurements of pyridine. The best enhancement of the signal was achieved using sample reduced and stabilized with citrate, with the particle size of approximately 40 nm and non-uniform distribution. As aggregating agents NaNO3, KCl and KBr in different concentrations were tested. The Raman signal for pyridine was enhanced even more with the addition of sodium borohydride instead of other aggregating agents. Addition of borohydride had the largest impact to sample stabilized with DEAE-dextran which consists of large (0.5 µm) as well as very small silver nanoparticles. The mixture colloid-borohydride-pyridine was stable for hours. 3. H. Gebavi, D. Ristić, V. Đerek, L. Mikec, M. Ivanda (Institute Ruder Boskovic, Zagreb, Croatia), D. Milanese (Politecnico di Torino, Torino, Italy) Raman spectroscopy of tellurite glasses  Tellurite glasses are known as a promising material for optical fiber fabrication thanks to the specific optical and thermo-mechanical features. This paper shows tellurite glasses doped with different concentrations of various rare earth ions characterized by Raman spectroscopy. Especial attention was paid to the low frequency ‘Boson peak’ and the modes of vibration which correspond to TeO4 and TeO3 structural units. The results show interesting correlation between structural order and rare earth ions concentration. 4. D. Ristić (Insitut Ruđer Bošković, Zagreb, Croatia), M. Mazzola, Italy), A. Chiappini, Italy), C. Armellini (CNR-IFN, Trento (TN), Italy), A. Rasoloniaina, P. Feron (ENSSAT-FOTON, Lannion, France), R. Ramponi (CNR-IFN, Milano, Italy), G. Nunzi-Conti, S. Pelli, G. Righini (CNR-IFAC, Firenze, Italy), G. Cibiel (CNES, Touluse, France), M. Ivanda (Insitut Ruđer Bošković, Zagreb, Croatia), M. Ferrari (CNR-IFN, Trento (TN), Italy) Coated spherical microresonators for cutting-edge photonics application  We present some results regarding the coating of spherical microresonators and their different applications in photonics. The spherical microresonators high Q-factor and low mode volume make them perfect for a number of photonics applications. A thin film coating on the surface of the resonator using an optically active or passive layer can be used to modify signifactly the optical properties of the resonator. We have succesfully coated the microresonators with a sol-gel derived coating and have studied the effect of the coating on different optical and spectroscopical properties of the microresonator. 5. B. Pejcinovic (Portland State University, Portland, Oregon, United States) Examination of silicon material properties using THz Time-Domain Spectroscopy  High-resistivity silicon is a very popular choice for substrate material when examining e.g. various thin films, biological samples etc. using THz radiation. This paper provides an overview of research on its THz properties, examines various practical issues appearing when determining its properties and reports results on complex index of refraction, permittivity and conductivity, obtained using modern instrumentation. Potential problems related to water absorption are highlighted. Various Drude models and parameters are also presented and discussed. 6. M. Poljak (Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia), M. Wang (University of California Los Angeles, Los Angeles, United States), S. Žonja (Faculty of Electrical Engineering and Computing, University of Zagreb, ZAGREB, Croatia), V. Đerek, M. Ivanda (Rudjer Boskovic Institute, Zagreb, Croatia), K. Wang (University of California Los Angeles, Los Angeles, United States), T. Suligoj (Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia) Impact of microstrip width and annealing time on the characteristics of micro-scale graphene FETs  Graphene field-effect transistors are fabricated using CVD-grown graphene and a wet transfer technique. Devices are characterized in terms of carrier mobility, contact resistance, output and transfer characteristics. We found that the mobility decreases and contact resistance increases with the decreasing graphene microstrip width. In addition, we found that graphene FET characteristics strongly depend on annealing time. The behavior of device characteristics is explained by discussing carrier scattering on defects and impurities, and the formation of pn-junctions in graphene. 7. S. Venica, F. Driussi, P. Palestri, L. Selmi (University of Udine, Udine, Italy) Graphene Base Transistors with optimized emitter and dielectrics  The Graphene Base Transistor (GBT) is a very promising device concept for analog applications. The device operates similar to the hot electron transistor and exploits the high carrier mobility of graphene to reduce the base resistance that limits the unity power gain frequency (fmax) and the noise figure (NF) of RF devices. Although the DC functionality of the GBT has been experimentally demonstrated, at present RF performance can be investigated by simulations only. In this paper, we predict the DC current and the cutoff frequency of different GBT designs (including dimensions and various materials), with the aim to optimize the GBT structure and to achieve THz operation. In particular, optimized emitter/dielectrics combinations are proposed to maximize RF figures of merit. 8. V. Ivanić (Department of Physics, Faculty of Science, University of Zagreb, Zagreb, Croatia), M. Poljak, T. Suligoj (Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia) Phonon-limited hole mobility in sub-20 nm-thick double-gate germanium MOSFETs  Physics-based modeling of hole mobilities in ultra-thin germanium layers is calculated with self-consistent Schödinger-Poisson solver and Kubo-Greenwood formula. Quantum confinement is taken into account for heavy, light and split-off hole band in a double-gate germanium MOSFET structure. Acoustic and optical phonon scattering is taken into consideration in the calculation of hole momentum relaxation time. The observed reduction of mobility in thinner layers is explained by examining the influence of field-induced and geometry-induced confinement. Contributions from different hole bands are investigated by calculating band population and respective band mobilities. 9. S. Krivec, Zagreb, Croatia), H. Prgić, Zagreb, Croatia), M. Poljak, Zagreb, Croatia), T. Suligoj (Faculty of Electrical Engineering and Computing (FER), Zagreb, Croatia) Comparison of RF performance between 20 nm-gate bulk and SOI FinFET  Due to their 3D architecture, FinFETs exhibit a strong dependence of RF figures-of-merit on device geometry due to large extrinsic resistances and capacitances. We analyze the RF performance of 20-nm gate length FinFETs implemented on either bulk or SOI substrate by using 3D numerical device simulation. SOI and bulk FinFET are compared in terms of cut-off and maximum oscillation frequency, gate capacitance and trans-conductance. We have proposed and investigated the influence of different doping methods that aim at improving the RF figures-of-merit of 20 nm bulk FinFETs while maintaining acceptable DC performance. Thursday, 5/29/2014 9:00 AM - 1:00 PM, Bellavista, Grand hotel Adriatic, Opatija Chair: Drago Resnik (Faculty of Electrical Engineering, University of Ljubljana, Slovenia)   Regular Papers  1. T. An, C. Hao, L. Naviner (Télécom ParisTech, LTCI, Paris, France) Simulation Study of Aging in CMOS Binary Adders  Hot carrier injection (HCI) and negative bias temperature instability (NBTI) become dominant reliability issues in nanometer CMOS technology. These aging effects can induce additional delay which will be accumulated through logic gates and thus degrade the performance of the circuits. This paper discusses performance degradations induced by aging mechanisms in digital integrated circuits. We propose an agingaware synthesis flow taking into account NBTI and HCI. This flow is demonstrated through the implementation of several architectures of adders using CMOS technology. The simulation results show that Kogge-Stone Adder (KSA) and SKlansky Adder (SKA) are the best solutions whether in terms of the complexity or the resistance to aging effects with induced delay degradation below 0.35%. 2. T. An, K. Liu, L. Naviner (Inisitut Mines-Télécom, Télécom ParisTech, Paris, France) Analytical method for reliability assessment of concurrent checking circuits under multiple faults  Reliability issues due to transient faults have increased with CMOS scaling and become an important concern for deep submicron technologies. Concurrent Error Detection (CED) scheme has been widely used against transient faults under the assumption of single fault and/or fault-free checking parts. In this work, we propose an analytical method in order to assess CED circuit reliability under more realistic hypothesis. In other words, we take into account occurrence of multiple faults and fault-prone checking parts. This method allows to demonstrate the efficiency of CED schemes. The computational requirements for such an assessment are reduced by progressive analysis of the overall circuit through conditional probabilities. The proposed solution has been demonstrated on classical CED schemes. 3. c. popa (University Politehnica of Bucharest, Bucharest, Romania) Synthesis of CMOS Multiplier Structures Using Multifunctional Circuits  The paper will present new high accuracy multiplier circuits, focused on the implementation of original techniques for improving the linearity of the proposed structures. The new approach of designing high precision multipliers using multifunctional cores presents the important advantage of allowing a facile reconfiguration of the designed circuits, the multiplier core being able to implement a multitude of additional circuit functions: amplifying, squaring and square-rooting or simulating a positive and negative equivalent resistance. The multiplier structures are designed for low-voltage low-power operation (the supply voltage is +/- 1.8V for implementing in 0.18um CMOS technology and the current consumption is smaller than 50uA for any proposed multiplier). 4. c. popa (University Politehnica of Bucharest, Bucharest, Romania) Improved Accuracy Current-Mode Analog Function Synthesizer  An original analog function synthesizer circuit with increased accuracy will be presented, allowing to implement a multitude of important continuous mathematical functions. The accuracy of the proposed structure is excellent and the range of the input variable is strongly extended as a result of the third-order approximation of the implemented functions. The circuit performance is expected to be stable against process corners as all functions exclusively depend on current ratios. The great advantages of the increased modularity and controllability and of the associated reduced design costs per function represent an immediate consequence of the multiple functions realized by the proposed structure. The function synthesizer circuit is designed for implementing in 0.18um CMOS technology and it is supplied at 1.8V. The SPICE simulations confirm the estimated theoretical results, showing an approximating error smaller than 0.01% for the composing squaring block and smaller than 0.013% for the composing multiplier/divider block. 5. S. Brenna (Politecnico di Milano, milano, Italy), A. Bonfanti, A. Abba, F. Caponio, A. Lacaita (Poliectnico di Milano, Milano, Italy) Analysis and optimization of a SAR ADC with Attenuation Capacitor  The conventional binary weighted array SAR ADC is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even requiring extra effort to design and simulate full custom sub-fF capacitors. This paper presents the design and the optimization of an asynchronous SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary weighted array converters but adopting standard MiM capacitors. A monotonic switching algorithm further reduces the capacitive array consumption while an asynchronous and fully-differential dynamic logic minimizes the digital power consumption. A 10-bit prototype has been fabricated in a 0.13-µm CMOS technology. At 0.5-V supply and 200-kSps sampling frequency, the ADC achieves a SNDR of 52.6 dB, an ENOB of 8.45, and a power consumption of 420 nW, corresponding to a figure-of-merit (FOM) of 6 fJ/conversionstep. This efficiency is comparable to the best results published so far and it’s the lowest among ADCs in 130-nm or less scaled technology. The ADC core occupies an area of only 0.045 mm^2 6. S. Brenna (Politecnico di Milano, milano, Italy), A. Bonetti (ams International AG, Rapperswil, Switzerland), A. Bonfanti, A. Lacaita (Politecnico di Milano, Milano, Italy) A Simulation and Modeling Environment for the Analysis and Design of Charge Redistribution DACs used in SAR ADCs  The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic effects in the feedback charge-redistribution DAC. Since the effects of both mismatch and stray capacitances depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a novel MATLAB-based numerical tool to assist the design of classic, split and with attenuation capacitor binary weighted capacitive array topologies with an even number of bits from 6 to 14. The tool allows to perform both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances in order to compute both differential- (DNL) and integral nonlinearity (INL). SNDR and ENoB degradation due to static non-linear effects is also estimated. An excellent agreement with the results obtained by the available circuit simulators (e.g. Cadence Spectre) is shown but featuring up to 10^4 shorter simulation time. 7. A. Najafi, S. Timarchi (Shahid Beheshti University, Tehran, Iran), A. Najafi (Islamic Azad University of Qazvin, Qazvin, Iran) High-speed Energy-efficient 5:2 Compressor  Multipliers are important components that dictate the overall arithmetic circuits’ performance. The most critical components of multipliers are compressors. In this paper, a new 5:2 compressor architecture based on changing some internal equations is proposed. In addition, using an efficient full-adder (FA) block is considered to have a high-speed compressor. The number of transistors in the proposed design is less than the best existing 5:2 compressor architectures. Three 5:2 compressors are considered for comparison. The proposed architecture is compared with the best existing designs presented in the state-of-the-art literature in terms of power, delay and area. Architectures are simulated in 90-nm CMOS technology under 1 V supply voltage. The simulation results show that the proposed compressor improves power and delay by 24.59% and 18.54% respectively, compared to two of the best existing architectures. In addition, voltage scaling and temperature analysis show that the proposed architecture outperforms the other designs from power-delay product (PDP) point of view in comparison to the aforementioned designs. 8. T. Kong Yew, Y. Yusoff, L. Kien Sieng, H. Che Lah, H. Majid, N. Shelida (Mimos Berhad, Kuala Lumpur, Malaysia) An electrochemical sensor ASIC for agriculture applications  This paper presents a fully integrated application specific integrated circuit (ASIC) for the readout of multiple electrochemical sensor signals. It consists of an analog router that routes readout circuits to various sensors, a 10-bit successive approximation register analog to digital converter (SAR ADC), two digital to analog converters (DAC), a multiplexer and I2C/SPI serial interfaces for connection to micro-controller (MCU). The ASIC is fabricated in a 0.35-μm CMOS technology, occupies an area of 1.5 × 3.0 mm2, and consumes a current of 3.2 mA from a 3.3 V supply. All calibration and configurations are set using the I2C/SPI serial interface connections. 9. A. Marinov, O. Stanchev, E. Bekov (Technical university of Varna, Varna, Bulgaria) Application of Charge Amplifiers with Polyvinylidene Fluoride Materials  The current paper proposes an improved specialized charge amplifier as an interface to measurement based applications that utilize Polyvinylidene Fluoride (PVDF) material. As this material and its interfacing electronics are still being researched, most of the applications and topologies are in development. PVDF material characteristics are reviewed and set as a basis for the design of the proposed charge amplifier. Experimental results of the proposed circuitry are compared to conventional voltage amplifiers. The charge amplifier characteristics and benefits are presented and discussed. Methodology for design of charge amplifier, applied to several measurement applications that utilize PVDF, is discussed. 10. T. Dolžan, D. Vrtačnik, D. Resnik, U. Aljančič, M. Možek, B. Pečar, S. Amon (University of Ljubljana, Faculty of Electrical Engineering, Laboratory of Microsensor Structures and, Ljubljana, Slovenia) Design of Transdermal Drug Delivery System with PZT actuated micropump  Investigation of transdermal drug delivery system, based on silicon injector chip with silicon microneedles and PZT(lead zirconate titanate) actuated micropump, for drug delivery such as insulinis reported. First, basic skin properties and dosing requirements are reviewed. Next, the whole system and its components (injector chip, micropump, drug container) are discussed. Based on this, microneedles injector chip design is discussed and prototypes fabricated. Then, design of PZT actuated micropumps is discussed and prototypes fabricated. From measurements on fabricated micropumps, fluidic parameters are evaluated. Basic requirements for drug container, control electronics and power supply parameters are also presented. Finally, maximum drug delivery, based on measured prototype micropump parameters, through the prototype injector chip is determined. Thursday, 5/29/2014 3:00 PM - 7:00 PM, Bellavista, Grand hotel Adriatic, Opatija Chair: Branimir Pejčinović (Portland State University, USA)   Regular Papers  1. J. Turán, Ľ. Ovseník (Technical University of Košice, Košice, Slovakia) Modern Monitoring System for Water Pollution by Petrochemical Products based on Optical Fibre Refractometer  Modern industrial quality monitoring systems are based on optical fibre sensors, microelectronic sensory technology and miniaturized infrared spectroscopy systems based on low-power, low-cost, high-efficient and innovative hardware solutions. The proposed paper presents development work related to create remote control system for monitoring water pollution petrochemical products using optical fibre refractometer. 2. M. Magerl, T. Mandic, A. Baric (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Broadband Characterization of SMA Connectors by Measurements  This paper presents the characterization of various types of SubMiniature version A (SMA) connectors. The characterization is performed by measurements in frequency and time domain. The SMA connectors are mounted on microstrip (MS) and conductor-backed coplanar waveguide (CPW-CB) manufactured on high-frequency (HF) laminates. The designed characteristic impedance of the transmission lines is 50 Ω and deviation from the designed characteristic impedance is measured. The measurement results suggest that for a given combination of the transmission line and SMA connector, the discontinuity in terms of characteristic impedance can be significantly improved by choosing the right connector type. 3. K. Ivanuš (KONČAR-Electrical Engineering Institute, Zagreb, Croatia), A. Barić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Application of TEM Cell in Measurement of Electromagnetic Fields of Electronic Modules  The paper presents measured radiated emissions of an electronic module in the frequency range 150 kHz – 200 MHz using the TEM cell method. The TEM cell measurement method is explained and measurement results for different orientations of the electronic module are presented. An explanation for the differences in the measured radiated emissions for different module orientations is given. 4. D. Nagradic (University of Zagreb/Faculty of Electrical Engineering and Computing, Zagreb, Croatia), K. Pardon (Systemcom Ltd., Zagreb, Croatia), D. Jurisic (University of Zagreb/Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Model of Low-Noise, Small-Current-Measurement System Using MATLAB/Simulink Tools  In this paper the model of a system for measuring small currents, which generates the digital signal proportional to the input current, was designed. The analysed measuring system is the part of a larger microelectronic mixed-signal integrated chip (SoC – System on Chip), and it is located between the input sensor and the external digital device. Since the part that mostly contributes to the noise inside the whole measuring chain is at the input of the chain, the measurement method is analyzed to minimize the impact of noise. Because the noise is not definite, the simulation of measurement by the model was made using statistical principles. Performing multiple measurements of the input value (in our example it is current Id) it is possible to calculate its mean value and standard deviation. It was shown that the measured quantity can be calculated from the mean value and that the standard deviation represents an amount of noise. Depending on the standard deviation it is needed to do either less or more sequential measurements to determine the reliable measured output digital value. 5. I. Sirotić, V. Šunde, Ž. Ban (Fakultet elektrotehnike i računarstva, Zagreb, Croatia) Algorithm for Fast Determination of LiFePO4 Battery Nominal Current  The development of production and increasing usage of light electric vehicles such as electric bicycles and electric scooters entails development of batteries, battery chargers and fast charging algorithms. Batteries with different nominal electrical characteristics and production technologies are currently in use. Among them, lithium - iron batteries are increasingly being used. The differences in basic characteristics of batteries and standardization issues require fast identification of various battery types and adapting of charging algorithms according to nominal current, voltage, capacity and state of charge. This paper describes a method for determining the nominal current for unknown LiFePO4 battery connected to the stationary filling station for charging electric bicycles. A prerequisite for determination of the rated current is identification of current-voltage curve at the moment of connection and identification of the number of cells. The algorithm for determining these parameters is given in the first part of the paper. The second part deals with determination of the nominal current for LiFePO4 battery based on current-voltage response to the selected battery charging algorithm. 6. D. Vinko, G. Horvat (Faculty of Electrical Engineering, Osijek, Croatia) 100 nA Power Management Circuit for Energy Harvesting Devices  This paper presents a power management circuit suitable for energy harvesting devices. Energy harvesting devices use various methods to generate useful energy from their surroundings. Harvesting energy from RF radiation, mechanical vibration, ambient light and other energy harvesting methods provides very low instantaneous power. In general, it is not possible to continuously power a wireless sensor node, which is the most common user of harvested energy. Instead, the harvested energy is collected over a longer period of time, and when sufficient energy is stored, it is used to power a wireless sensor node for a short time interval. To accomplish that, a power management circuit with ultra-low power consumption is needed. Presented power management circuit is designed to turn on the wireless sensor node when the voltage across storage capacitor reaches 5.5 V and turns it back off as the voltage drops to 4.5 V. In such operating conditions the maximal current that power management circuit draws is under 50 nA. Laboratory model of the power management circuit is realized and its performances under various input conditions are measured. Additionally, a mathematical model of the power management circuit is derived and compared with measurement results. 7. J. Bačmaga, K. Bene (Fakultet elektrotehnike i računarstva, Zagreb, Croatia), B. Pejcinovic (Portland State University, Portland, Oregon, United States), A. Barić (Fakultet elektrotehnike i računarstva, Zagreb, Croatia) Evaluation of the operation of Depletion-mode SiC Power JFET in DC-DC converter applications  This paper presents the system for the evaluation of operation of a depletion-mode silicon carbide (SiC) power junction field-effect transistor (JFET). The main part of the system is a dc-dc step-down converter which represents realistic operating conditions for the switching devices in a synchronous buck configuration. In order to test the importance of the dead-time value on the operation and efficiency of the synchronous buck converter, a precise two-cahnnel time-delay pulse signal generator is developed and its operation is described. The ability to precisely regulate control signal parameters of the high-side FET and low-side FET (switching voltage and current, operating frequency, duty cycle, dead-times, etc.) is needed in order to fully characterise SiC power switches. The functionality of the complete system is verified by measurements performed under various operating conditions. 8. K. Fukuda (CANON.INC, Toride-shi, Japan), V. Čeperić, A. Barić (University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Photocopier PID Controller with Iterative Error Compensation  This paper describes an implementation of a proportional-integral-derivative (PID) controller with an iterative error compensator for a DC brushless motor to improve the quality of a photocopier. The parameters of the iterative error compensator are determined by using particle swarm optimization algorithm. The proposed controller reduces the effects of repetitious unknown load torque on the DC brushless motor by compensating the motor torque based on the motor velocity from the previous sequences. The proposed controller is compared to a PID controller under various load torques. 9. J. Podrzaj, G. Babic, M. Podhraski (Letrika Lab d.o.o., Sempeter pri Gorici, Slovenia), J. Trontelj (University of Ljubljana, Faculty of Electrical Eng., Ljubljana, Slovenia) Introduction of Some Design Aspects for Improved Performance of the DC/AC Induction Motor Converter  The increasing trend of DC/AC induction motor converters implementation in a wide range of driving applications is becoming a fact that could not be neglected any more. This fact challenges the designers of the DC/AC induction motor converters to constantly seek performance improvements and cost reductions on an everyday basis. The paper describes some of the design improvements of a DC/AC induction motor converter for use in light commercial electrical vehicles. The implementation of design changes is based on electrical analysis, simulation results and also on the previous prototype testing. The goal of design activity presented in the paper is a design of an improved DC/AC induction motor converter with higher performance, enhanced reliability and optimized production cost. The paper concludes with a proposal of a new DC/AC induction motor converter design and concludes with some simulation results. 10. J. Divić, J. Đurić, K. Vrančić (Visoka škola za informacijske tehnologije Zagreb, Zagreb, Croatia) Microcontroller implementation of dynamically adaptable control of stepper motor with continuous second derivative of speed curve  Stepper motor controll is well known and in literature thoroughly described subject for parameters of position, speed and acceleration. Stepper motor speed control with dinamicaly adoptable parameters of target speed and maximal alowed acceleration, requireing continuous change of acceleration (continous second derivation of speed function)presents challenge to microcontroller implementation on factors of processing power and/or available memory array. Authors failed to find this kind of algorithm described in available literature, and consider it important for practical solutions of speed control in phisical systems susceptable to oscillations. Paper offers theoretical basics, illustrates example of phisical system susceptable of unwanted oscillations, and presents example of algorithm. Friday, 5/30/2014 9:00 AM - 1:00 PM, Bellavista, Grand hotel Adriatic, Opatija Chair: Željko Butković (Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia)   Regular Papers  1. N. Mijat, D. Jurišić (Faculty of Electrical Engineering and Computing, Zagreb, Croatia) Optimized Coupled Band-Pass Filters  In this paper we compare two versions of fourth-order band-pass (BP) filter section realized as coupled structure, having negative feedback around two Biquadratic sections in cascade, usually designated as Biquartic section (i.e. it is the fourth-order band-pass section). The frequency response of a filter is subject to vary from the nominal values due to the effects of aging, changing working conditions, the fabrication tolerances of passive and active elements, etc. In order to maintain the filter’s characteristics inside given specifications at the time of manufacture, and as long as possible, the main requirement is to design filters with reduced sensitivity to component tolerances. The Biquartic section has significantly reduced sensitivities to the changes of passive element values, particularly within the pass band, in comparison to common cascade design. For that purpose this structure is very suitable for use as a building block of narrow band, high order BP filters. The sensitivities are further reduced by using three-amplifier biquadratic block instead of more sensitive single-amplifier block. We investigated the sensitivities of two versions of biquartic section with two extreme combinations of second-order sections q-factor values, using Schoeffler’s measure, the dynamic range, and output thermal noise using analysis in PSpice. Biquartic sections used throughout the examples are realized as reduced amplifier version retaining the low sensitivities of biquartic design. They also possess simple tuning features and simple design; design equations are given. 2. T. Čihak, M. Puškarić (KONČAR-Institut za elektrotehniku d.d., Zagreb, Croatia), Ž. Jakopović (Fakultet elektrotehnike i računarstva, Zagreb, Croatia) Development and testing of complex PLL algorithm using hardware in the loop system  Grid connected converters present a key element in modern systems for harvesting renewable energy sources. Each of these converters, non-dependent on the converter topology, requires a grid synchronization algorithm. This is not a new requirement for such converter types, but design and development of applicable algorithms requires a lot of time and resources. This is especially evident in high power converters on which grid codes are applied. This paper shows an accelerated development method applied on a complex PLL structure resulting with a code suitable for deployment on real-time control system. 3. C. Sandu, I. Florescu, C. Rotaru (University POLITEHNICA , Bucharest, Romania) Software Simulation of LDPC Codes and Performance Analysis  In this paper we will analyze the influence of using LDPC codes in different channels environment. The performances of LDPC codes are estimated in several scenarios. The simulation software gives us the possibilities to choose between different communications channels according to the encoding matrix used. Also we can adjust a number of parameters, thing that help to find the optimal solution depending on the decoding error rate or Bit Error Rate (BER). Optimal combinations between parameters, the encoding matrix and structures design are obtained, related to required performance or Signal Noise Ratio (SNR) ranges. The sets of parameters and criteria introduced are discussed as the simulation results, also. 4. N. Skeledžija, J. Ćesić, E. Kočo, V. Bachler, H. Vučemilo, H. Džapo (Fakultet elektrotehnike i računarstva, Zagreb, Croatia) Smart Home Automation System for Energy Efficient Housing  This paper presents a concept and implementation of modern smart monitoring and control system for building automatization. The system is designed to enable significant reduction of energy consumption and carbon footprint by increasing the energy efficiency of the building under control. The system consists of a Linux-based remotely accessible main embedded control unit, a custom designed programmable logic controller named littlePLC, and a propriatery low-power Wireless Sensor Network (WSN). The energy flow is optimized by using a Model Predictive Control (MPC) algorithm that runs on the main control unit. The main control unit communicates with littlePLC, which serves as an interface that controls the parameters and state of HVAC systems in the building. The feedback information for MPC is gathered by means of the WSN, which consists of various sensor node types, such as temperature, air pressure, humidity, VOC and CO2. The WSN nodes are connected in a star type network topology, with a communication HUB connected to the main control unit. The information gathered by WSN are used in the MPC algorithm in order to calculate and estimate the requirements for heat corrections, with respect to ventilation and weather predictions. 5. K. Saksida, A. Trost (University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia) Remote Laboratory for Testing Processor Cores in FPGA Device  In the paper we present generic hardware verification structures for efficient testing of the custom processor cores in FPGA devices. Hardware verification environment consists of hardware debug structures: control machine, memory access port, input and output data buffers and interface logic. The verification structures are integrated and synthesized with the processor core under test and implemented on the FPGA device. The structures can be customized and easily integrated in the hardware development flow. A software support for the hardware verification consists of a data acquisition driver running on the server with HTML5 graphical interface. The software enables either local testing or setup of a remote laboratory for testing of the processor cores. The application of the remote laboratory in the educational process is presented. The presented hardware verification structures are optimized for testing the soft programmable processor cores and are vendor independent. The software support is based on open languages and protocols and the scripting tools enable quick customization. We present advantages of our solution compared to commercial general purpose on-chip logical analyzers. The benefit of our approach is that it can be used with the standard programmable design tools on the low cost platforms and provides two abstraction levels of debugging. 6. Z. Krpić, G. Horvat, D. Žagar, G. Martinović (Faculty of Electrical Engineering, Osijek, Croatia) Towards an energy efficient SoC computing cluster  High performance computing (HPC) systems are omnipresent in processing huge amounts of data. However, power consumption of these systems is becoming far from negligible, forcing software developers and hardware providers to deviate from usual performance plans, and to address power consumption and costs. As a result, small-scale applications are becoming infeasible to run on those systems, making room for the power-efficient HW newcomers, such as SoCs, to take that role. The idea of composing a large number of small SoCs in a computing cluster can result in a powerful, green, and a simple platform capable of delivering enough performance for the small applications while maintaining low energy consumption and costs. In this paper we present a system composed of four LAN-interconnected dual-core ARM based SoC devices, powered by a single power supply. We investigate applicability of such a system by monitoring its performance and energy efficiency and stability while using common HPC paradigms: message passing and thread programming. 7. L. Perković, D. Kovačević, T. Karađole, M. Jović (Pomorski fakultet Split, Split, Croatia) Electronic interpretation of selected lessons in fuzzy mathematics  Dedicated electronic hardware has been used to interpret selected lessons in fuzzy mathematics. DeMorgans Laws were simulated in an electronic environment and that simulation was then used as a base to illustrate how the law of excluded middle is violated by fuzzy sets. In that context the problem of fuzzy grade of inclusion is briefly analysed and simulated electronically. 8. D. Kovačević, T. Karađole, J. Vrsalović (Pomorski fakultet Split, Split, Croatia) Fuzzy gates interchangeability  The idea of this paper is related to possible conversions of min, max and mid fuzzy gates functions. If we want to convert basic min and max gate function to another logical function, for some reason, that can be done on several ways. For the beginning one can convert only gate inputs. In the second case only gate outputs can be inverted. The third kind of the gate interchangeability is done by the combination of inverting inputs and outputs. At the end, it is possible to design min, max and mid gates to be controllable through gate inputs information (inputs voltages). 9. I. Madunić, D. Kovačević, L. Perković, T. Karađole (Pomorski fakultet Split, Split, Croatia) Solving mathematic problems in electronic environment; finding global and local minimum and maximum function values  A dedicated Hardware simulation tool is used to solve specific mathematical as well as electronic problem: finding global minimum and maximum function values (coordinates in Cartesian coordinate system). A new class of peak detector based on fuzzy min and max gates has been proposed. Hardware methods, having pure mathematical background, in detecting x-coordinates of function extrems are explained, too.

 

Željko Butković (Croatia), Petar Biljanović (Croatia)

Slavko Amon (Slovenia), Dubravko Babić (Croatia), Maurizio Ferrari (Italy), Mile Ivanda (Croatia), Branimir Pejčinović (United States), Aleksandar Szabo (Croatia), Baldomir Zajc (Slovenia)

Petar Biljanović (Croatia)

Alberto Abello Gamazo (Spain), Slavko Amon (Slovenia), Vesna Anđelić (Croatia), Michael E. Auer (Austria), Mirta Baranović (Croatia), Ladjel Bellatreche (France), Eugen Brenner (Austria), Andrea Budin (Croatia), Željko Butković (Croatia), Željka Car (Croatia), Matjaž Colnarič (Slovenia), Alfredo Cuzzocrea (Italy), Marina Čičin-Šain (Croatia), Marko Delimar (Croatia), Todd Eavis (Canada), Maurizio Ferrari (Italy), Bekim Fetaji (Macedonia), Tihana Galinac Grbac (Croatia), Liljana Gavrilovska (Macedonia), Matteo Golfarelli (Italy), Stjepan Golubić (Croatia), Francesco Gregoretti (Italy), Stjepan Groš (Croatia), Niko Guid (Slovenia), Yike Guo (United Kingdom), Jaak Henno (Estonia), Ladislav Hluchy (Slovakia), Vlasta Hudek (Croatia), Željko Hutinski (Croatia), Mile Ivanda (Croatia), Hannu Jaakkola (Finland), Leonardo Jelenković (Croatia), Dragan Jevtić (Croatia), Robert Jones (Switzerland), Peter Kacsuk (Hungary), Aneta Karaivanova (Bulgaria), Dragan Knežević (Croatia), Mladen Mauher (Croatia), Igor Mekjavic (Slovenia), Branko Mikac (Croatia), Veljko Milutinović (Serbia), Alexandru-Ioan Mincu (Slovenia), Vladimir Mrvoš (Croatia), Jadranko F. Novak (Croatia), Jesus Pardillo (Spain), Nikola Pavešić (Slovenia), Vladimir Peršić (Croatia), Goran Radić (Croatia), Slobodan Ribarić (Croatia), Janez Rozman (Slovenia), Karolj Skala (Croatia), Ivanka Sluganović (Croatia), Vlado Sruk (Croatia), Uroš Stanič (Slovenia), Ninoslav Stojadinović (Serbia), Jadranka Šunde (Australia), Aleksandar Szabo (Croatia), Laszlo Szirmay-Kalos (Hungary), Davor Šarić (Croatia), Dina Šimunić (Croatia), Zoran Šimunić (Croatia), Dejan Škvorc (Croatia), Antonio Teixeira (Portugal), Edvard Tijan (Croatia), A Min Tjoa (Austria), Roman Trobec (Slovenia), Ivana Turčić Prstačić (Croatia), Sergio Uran (Croatia), Tibor Vámos (Hungary), Mladen Varga (Croatia), Marijana Vidas-Bubanja (Serbia), Boris Vrdoljak (Croatia), Robert Wrembel (Poland), Baldomir Zajc (Slovenia), Damjan Zazula (Slovenia)

Željko Butković
Faculty of Electrical Engineering and Computing
Unska 3
HR-10000 Zagreb, Croatia

Phone: +385 1 6129 924, GSM: +385 98 951 7179
Fax: +385 1 6129 653
E-mail: zeljko.butkovic@fer.hr

Opatija – the cradle of European and Croatian tourism, a favourite destination of the aristocracy, film and music stars, artists, writers and visitors from all over the world, who come here every year to enjoy the charm of this Adriatic town – this year celebrates its 170th anniversary as a tourist resort.

This is a tradition that provides certain obligations, but is also a guarantee of quality. The reputation of a top destination that stretches back seventeen decades is today reflected in the wide range of facilities and services on offer that all together make Opatija an attractive destination for all seasons.

Opatija owes its unique image to its ideal location on the spot where the wooded slopes of Mount Učka descend all the way down to the coast, providing perfect shade along the thirteen-kilometre-long Lungomare seafront promenade. Just as the Opatija area is a meeting point of the sea and the mountain, its visual impression is a blend of different styles, as this is a melting pot where magnificent Central European elegance, playful Mediterranean charm and the historically-rich medieval architecture of the small towns in the hinterland come together. 

In addition to the architecture that leaves a strong impression on every visitor, especially when the town is viewed from the sea, and its lush parks and gardens that have been Opatija's trademarks since its beginnings as a tourist resort, Opatija also has hotels and restaurants whose quality ranks alongside that of any other European destination. Opatija's gastronomic offer is based on a Mediterranean cuisine rich in fresh fish and seafood and locally grown seasonal ingredients, while the traditional recipes of this region reveal a wealth of flavours and can be sampled in the area's numerous taverns. 

Opatija entered the European stage in the mid-19th century as a health resort for the European nobility, and health tourism has remained one of the main segments of the town's tourism offer right up to the present day. However, top medical experts and a wide range of spa & wellness services are just one of the reasons for visiting this town located at the top of Kvarner Bay. Also known as "the town of festivals", Opatija boasts a number of events throughout the year. The theatrical performances and concerts that take place at the magnificent Open Air Theatre are particularly impressive.

For more details please look at www.opatija.hr/ and www.opatija-tourism.hr/.